Semiconductor device and fabrication method

ABSTRACT

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is based upon, and claims the benefit ofpriority of Japanese Patent Application No. 2011-84093 filed on Apr. 5,2011, and Japanese Patent Application No. 2012-000836 filed on Jan. 5,2012, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor deviceand a method for fabricating the semiconductor device.

BACKGROUND

In a typical metal-oxide semiconductor (MOS) transistor, one of a sourceregion and a drain region is formed in a reverse conducting well thatforms a device region. In such a configuration, the source region or thedrain region is isolated by a p-n junction from the well formed at aninterface between the source region and the well or between the drainregion and the well.

However, in the typical MOS transistor, an operating speed may bereduced due to a parasitic capacitance of the p-n junction and currentleakage may be easily generated.

Thus, there is proposed a metal-oxide-semiconductor (MOS) transistorstructure in which wells are separated by an insulator structure such asoxide films, nitride films or voids that are locally formed beneath thesource region or the drain region in the device region. Such a MOStransistor structure may be capable of reducing the junction capacitanceor reducing the leakage of current.

Japanese Laid-open Patent Publication No. 2009-10040 disposes an exampleof a process for forming the MOS transistor structure. The disclosedprocess for forming the MOS transistor structure includes forming alayered structure having a SiGe mixed crystal layer and a Si layer onthe SiGe mixed crystal layer, and removing the SiGe mixed crystal layeralone utilizing the etching rate difference between the Si layer and theSiGe mixed crystal layer. Silicon oxide film embedded regions may belocally formed immediately beneath the source region or the drain regionby filing the voids after the SiGe mixed crystal layer has been removed,and hence, the silicon-on-insulator (SOI) structure may be formedlocally.

RELATED ART DOCUMENT

-   Patent Document 1: Japanese Laid-open Patent Publication No.    2009-10040-   Patent Document 2: Japanese Laid-open Patent Publication No.    2011-3788-   Non-Patent Document 1: Kim, Y. S., et. al., IEDM Tech. Dig., pp.    871-874, 2006

In an example, a trench is formed on each side of a channel region in asilicon substrate, the trenches are filled with the layered structurehaving a SiGe mixed crystal layer formed on the Si layer, and then theSiGe mixed crystal layer is selectively removed by etching.

However, with such a process in the example, side surfaces of the trenchmay be covered while the SiGe mixed crystal layer is formed. As aresult, the Si layer formed on the SiGe mixed crystal layer may notdirectly be formed on the side walls of the trench but indirectly beformed on the side walls of the trench via the SiGe mixed crystal layer.

If the SiGe mixed crystal layer is selectively removed in such astructure, the Si layer formed on the SiGe mixed crystal layer may losea mechanical support, and the Si layer may be formed corresponding tothe SiGe mixed crystal layer such that the Si layer falls in the voidswhere the oxide film is yet to be embedded.

SUMMARY

According to an aspect of an embodiment, a semiconductor device thatincludes a semiconductor substrate including a well having a firstconductivity type, the well being defined by a device isolation region;a gate insulating film formed on the semiconductor substrate; a gateelectrode formed on the gate insulating film, the gate electrodeincluding a first side surface and a second side surface facing thefirst side surface; and a first side wall insulating film formed on thefirst side surface and a second side wall insulating film formed on thesecond side surface. In the semiconductor device, the semiconductorsubstrate includes a mesa structure located below the first side wallinsulating film, the gate electrode and the second side wall insulatingfilm, the mesa structure includes a first side surface and a second sidesurface, a first semiconductor layer having the second conductivity typethat form a source region is formed outside of the first side surface ofthe mesa structure, with the first semiconductor layer being connectedto the semiconductor substrate on the first side surface, a secondsemiconductor layer having the second conductivity type that form adrain region is formed outside of the second side surface of the mesastructure, with the second semiconductor layer being connected to thesemiconductor substrate on the second side surface, a first embeddedinsulating region formed of a first insulating film is formed beneaththe first semiconductor layer and a second embedded insulating regionformed of the first insulating film is formed beneath the secondsemiconductor layer, and a second insulating film is formed between thefirst embedded insulating region and the first side surface of the mesastructure, and a third insulating film is formed between the secondembedded insulating region and the second side surface of the mesastructure.

The object and advantages of the invention will be realized and attainedby means of the elements and combinations particularly pointed out inthe appended claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

Additional objects and advantages of the embodiments will be set forthin part in the description which follows, and in part will be obviousfrom the description or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a first embodiment;

FIG. 1B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1C is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1D is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1E is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1F is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1G is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1H is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1I is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1J is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1K is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1L is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1M is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1N is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1O is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1P is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1Q is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1R is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1S is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 1T is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the first embodiment;

FIG. 2A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a modification of thefirst embodiment;

FIG. 2B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the modification ofthe first embodiment;

FIG. 3A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a second embodiment;

FIG. 3B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3C is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3D is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3E is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3F is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3G is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3H is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3I is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3J is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3K is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3L is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3M is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3N is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3O is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3P is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3Q is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3R is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3S is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3T is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3U is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3V is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3W is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 3X is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the second embodiment;

FIG. 4A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a third embodiment;

FIG. 4B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the third embodiment;

FIG. 4C is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the third embodiment;

FIG. 5A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a modification of thethird embodiment;

FIG. 5B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the modification ofthe third embodiment;

FIG. 5C is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the modification ofthe third embodiment;

FIG. 6A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a modification of thefirst embodiment;

FIG. 6B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the modification ofthe first embodiment;

FIG. 7A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a fourth embodiment;

FIG. 7B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7C is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7D is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7E is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7F is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7G is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7H is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7I is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7J is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7K is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7L is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7M is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7N is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7O is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7P is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7Q is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 7R is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the fourth embodiment;

FIG. 8A is a cross-sectional diagram illustrating a method forfabricating a semiconductor device according to a modification of thefourth embodiment; and

FIG. 8B is a cross-sectional diagram illustrating the method forfabricating the semiconductor device according to the modification ofthe fourth embodiment.

DESCRIPTION OF EMBODIMENTS

In the following, a description is given, with reference to theaccompanying drawings, of embodiments. Initially, a method forfabricating a MOS transistor according a first embodiment is describedwith reference to FIGS. 1A to 1T.

First Embodiment

As illustrated in FIG. 1A, a p-well 11PW is formed in a flat substratesurface, such as a (100) plane, of a silicon substrate 11 formed ofsingle crystal bulk silicon by doping boron (B) or the like in a deviceregion 11B of the silicon substrate 11 in which an n-channel MOStransistor is to be formed at an accelerating energy of 300 keV or lowerat a dose of 5×10¹³ or lower, or preferably at an accelerating energy of150 keV at a dose of 3×10¹³, while a device region 11A of the siliconsubstrate 11 in which a p-channel MOS transistor is to be formed iscovered with a not illustrated photoresist pattern. The ions may beimplanted at any tilt and in one or more incident directions (directionsof twist), and examples of the ions to be implanted may be one or moretypes of ions such as BF₂ and In other than B.

In this case, B may be doped in the device region 11B of the siliconsubstrate 11 at an accelerating energy of 150 keV or lower at a dose of1×10¹³ cm⁻² or lower, or preferably at an accelerating energy of 30 keVat a dose of 5×10¹² cm⁻² so as to perform channel stop implantation. Theions may be implanted to perform the channel stop implantation at anytilt and in one or more incident directions (directions of twist), andexamples of the ions to be implanted may be one or more types of ionssuch as BF₂ and In other than B.

Next, ions are implanted for adjusting a threshold of the n-channel MOStransistor. For example, B may be doped at an accelerating energy of 40keV or lower at a dose of 3×10¹³ cm⁻² or lower, or preferably at anaccelerating energy of 20 keV at a dose of 1×10¹³ cm⁻². In this case,the ions may be implanted at any tilt and in one or more incidentdirections (directions of twist). Further, examples of the ions to beimplanted may be one or more types of other B molecular ions such as In,BF₂ and B₁₀Hx other than B.

The photoresist pattern formed in the device region 11A of the siliconsubstrate 11 is subsequently removed by an asking process or a wetprocess utilizing a sulfuric acid hydrogen peroxide mixture (SPM) or thelike. Thereafter, an n-well 11NW is formed in the device region 11A ofthe silicon substrate 11 while the device region 11B of the siliconsubstrate 11 is covered with the photoresist pattern, in a similarmanner as a process of forming the p-well 11PW.

More specifically, the n-well 11NW is formed by doping phosphorus (P) orthe like as an impurity element in the device region 11A of the siliconsubstrate 11 at an accelerating energy of 600 keV or lower at a dose of5×10¹³ cm⁻² or lower, or preferably at an accelerating energy of 350 keVat a dose of 3×10¹³ cm⁻². The ions may be implanted at any tilt and inone or more incident directions (directions of twist), and examples ofthe ions to be implanted may be one or more types of ions such asarsenic (As) and antimony (Sb) other than P.

In this case, As may be doped in the device region 11A of the siliconsubstrate 11 at an accelerating energy of 300 keV or lower at a dose of1×10¹³ cm⁻² or lower, or preferably at an accelerating energy of 100 keVat a dose of 5×10¹² cm⁻² so as to perform channel stop implantation. Theions may be implanted at any tilt and in one or more incident directions(directions of twist), and examples of the ions to be implanted may beone or more types of ions such as As and Sb other than P.

Next, ions are implanted for adjusting a threshold of the p-channel MOStransistor. For example, As may be doped at an accelerating energy of200 keV or lower at a dose of 3×10¹³ cm⁻² or lower, or preferably at anaccelerating energy of 130 keV at a dose of 3×10¹³ cm⁻². The ions may beimplanted at any tilt and in one or more incident directions (directionsof twist), and examples of the ions to be implanted may be one or moretypes of ions such as P, As and Sb.

The photoresist pattern formed in the device region 11B of the siliconsubstrate 11 is subsequently removed by an asking process or a wetprocess utilizing a sulfuric acid hydrogen peroxide mixture (SPM) or thelike. Thereafter, the silicon substrate 11 is spike annealed at 1000° C.or the like for approximately 10 sec to activate the impurity elementsuch as B, P or As doped in the silicon substrate 11.

Note that in the above description, the well implantation or the channelimplantation is initially performed in the process illustrated in FIG.1A; however, the well implantation or the channel implantation may beperformed after forming the later-described a shallow trench isolation(STI) structure.

Next, as illustrated in FIG. 1B, an oxide film is formed on the siliconsubstrate 11 by chemical vapor deposition (CVD) process, and the oxidefilm is then patterned to thereby form oxide film patterns 11Ox₁ and11Ox₂ in a substrate part 11CH₁ forming a channel region of thep-channel MOS transistor and a substrate part 11CH₂ forming a channelregion of the n-channel MOS transistor, respectively. Further, thesilicon substrate 11 is subject to dry etching utilizing an etching gassuch as Cl₂ or HCl while utilizing the oxide film patterns 11Ox₁ and11Ox₂ as a mask. As a result, trenches TA₁ to TA₃ having a depth rangeof 40 to 150 nm are formed at each side of the substrate part 11CH₁ andeach side of the substrate part 11CH₂ of the silicon substrate 11. InFIG. 1B, each of the substrate part 11CH₁ and the substrate part 11CH₂may have a width range of 30 to 100 nm.

As a result of having formed the trenches TA₁ to TA₃, the substrate part11CH₁ and the substrate part 11CH₂, on which the oxide film patterns11Ox₁ and 11Ox₂ are respectively formed, each form a mesa structure.Note that the substrate part 11CH₁ and the substrate part 11CH₂ extendupwardly from the silicon substrate 11 as a part of the siliconsubstrate 11.

Next, as illustrated in FIG. 1C, an insulating film 11TOx such as asilicon oxide film, a silicon nitride film or a silicon oxynitride(SiON) film is uniformly deposited on the obtained structure illustratedin FIG. 1B by a vapor-phase deposition process such as the CVD processor an atomic layer deposition (ALD) process. The insulating film 11TOxmay preferably have a film thickness of 10 nm or less. Note that a filmthickness of 2 nm may be a sufficient thickness of the insulating film11TOx. The insulating film 11TOx is uniformly formed such that surfacesof the oxide film patterns 11Ox₁ and 11Ox₂, and bottom surfaces and sidesurfaces of trenches TA₁, TA₂ and TA₃ are covered with a uniformthickness of the insulating film 11TOx.

Next, as illustrated in FIG. 1D, anisotropic etching is performed on theobtained structure illustrated in FIG. 1C by reactive-ion etching (RIE)that reacts approximately perpendicular to the surface of the siliconsubstrate 11. As a result, the insulating film 11TOx is removed from thebottom surfaces of the trenches TA₁ to TA₃ such that the siliconsubstrate 11 is exposed from the bottom surfaces of the trenches TA₁ toTA₃. Note that in the obtained structure illustrated in FIG. 1D, theinsulating film 11TOx is removed from the surfaces of the oxide filmpatterns 11Ox₁ and 11Ox₂, and hence, the insulating film 11TOx remainsonly on the side surfaces of the trenches TA₁, TA₂ and TA₃.

Next, as illustrated in FIG. 1E, SiGe mixed crystal layers 11SG₁ to11SG₃ having a thickness range of, for example, 20 to 80 nm selectivelyand epitaxially grow on the exposed surface of the silicon substrate 11,namely, the bottom surfaces of the trenches TA₁ to TA₃ by the CVDprocess utilizing a mixed gas of silane (SiH₄), dichlorosilane(SiH2Cl₂), monogermane (GeH₄), hydrogen chloride (HCl) and hydrogen (H₂)while utilizing the oxide film patterns 11Ox₁ and 11Ox₂ as a mask. Notethat in the present specification, the SiGe mixed crystal layerindicates a mixed crystal layer that may further include other elementsin addition to Si and Ge. Likewise, the SiC mixed crystal layerindicates a mixed crystal layer that may further include other elementsin addition to Si and C.

For example, the SiGe mixed crystal layers 11SG₁ to 11SG₃ mayepitaxially grow at a growth rate of 45 nm/min at a substratetemperature range of 650 to 750° C., or preferably at a substratetemperature of 700° C. by setting a partial pressure range of thehydrogen gas to 4000 to 6000 Pa, or preferably to 5300 Pa, by setting apartial pressure range of the dichlorosilane to 20 to 30 Pa, orpreferably setting a partial pressure to 26, by setting a partialpressure range of the monogermane to 10 to 15 Pa, or preferably settinga partial pressure to 12 Pa, and by setting a partial pressure range ofthe hydrogen chloride to 10 to 15 Pa, or preferably setting a partialpressure to 12 Pa under a pressure range of 1330 to 13300 Pa (i.e., 10to 100 Torr), or preferably under a pressure of 5320 Pa (i.e., 40 Torr).

Examples of the SiGe mixed crystal layers 11SG₁ to 11SG₃ include theatomic fraction of Ge of approximately 20%. However, the Ge compositionmay be increased within a range that allows the SiGe mixed crystallayers 11SG₁ to 11SG₃ to epitaxially grow on the exposed surface of thesilicon substrate 11. For example, the SiGe mixed crystal having theatomic fraction of Ge of approximately 40% may be utilized as the SiGemixed crystal layers 11SG₁ to 11SG₃. In addition, the SiGeC mixedcrystal layer obtained by further adding C to the SiGe mixed crystal mayalso be utilized as the SiGe mixed crystal layers 11SG₁ to 11SG₃.

As illustrated in FIG. 1E, in the first embodiment, the side surfaces ofthe trenches TA₁, TA₂ and TA₃ are covered with the insulating film11TOx. Accordingly, the SiGe mixed crystal layers 11SG₁ to 11SG₃ may nothave to cover the side surfaces of the trenches TA₁, TA₂ and TA₃.

Next, as illustrated in FIG. 1F, exposed parts of the insulating film11TOx, which covers the side surfaces of the trenches TA₁, TA₂ and TA₃,are removed by wet etching or dry etching so as to expose the siliconsubstrate 11 from the side surfaces of the trenches TA₁, TA₂ and TA₃. Asa result, as illustrated in an enlarged diagram indicated by a circle inFIG. 1F, an upper end of the insulating film 11TOx is located at aslightly depressed position from an upper end of the SiGe mixed crystallayers 11SG₁ to form a recess.

Next, as illustrated in FIG. 1G, silicon epitaxial layers 11ES₁ to 11ES₃are grown on the SiGe mixed crystal layers 11SG₁ to 11SG₃, respectively,utilizing a silane gas or a mixed gas of hydrogen chloride and hydrogenas a raw material so as to substantially fill the trenches TA₁, TA₂ andTA₃.

For example, the silicon epitaxial layers 11ES₁ to 11ES₃ may epitaxiallygrow at a growth rate of 0.7 nm/min at a substrate temperature range of650 to 750° C., or preferably at a substrate temperature of 700° C. bysetting a partial pressure range of the hydrogen gas to 4000 to 6000 Pa,or preferably to 5300 Pa, by setting a partial pressure range of thedichlorosilane to 15 to 25 Pa, or preferably setting a partial pressureto 21, and by setting a partial pressure range of the hydrogen chlorideto 3 to 10 Pa, or preferably setting a partial pressure to 5 Pa under apressure range of 1330 to 13300 Pa (i.e., 10 to 100 Torr), or preferablyunder a pressure of 5320 Pa (i.e., 40 Torr).

As a result, a layered structure composed of the SiGe mixed crystallayers 11SG₁ to 11SG₃ and the silicon epitaxial layers 11ES₁ to 11ES₃ isfilled in the space on each side of the substrate part 11CH₁ and thesubstrate part 11CH₂ each forming the mesa structure.

Thus formed silicon epitaxial layers 11ES₁ to 11ES₃ are epitaxiallybonded with the silicone substrate 11 and with the side surfaces of thetrenches TA₁ to TA₃.

Next, as illustrated in FIG. 1H, the oxide film patterns 11Ox₁ and 11Ox₂are removed and device isolation trenches 11TI₁ to 11TI₃ are formed inpredetermined device isolation regions by dry etching such that deviceisolation trenches 11TI₁ to 11TI₃ are formed deeper than bottom surfacesof the SiGe mixed crystal layers 11SG₁ to 11SG₃ to reach the siliconsubstrate 11 beneath the SiGe mixed crystal layers 11SG₁ to 11SG₃. As aresult, the SiGe mixed crystal layers 11SG₁ to 11SG₃ are exposed fromside surfaces of the device isolation trenches 11TI₁ to 11TI₃. Note thatthe device isolation trenches 11TI₁ to 11TI₃ illustrated in FIG. 1H areformed at an etching cone angle of several degrees towards a depthdirection (of the substrate 11). However, since the etching cone angleresults from an etching condition, the device isolation trenches 11TI₁to 11TI₃ may be formed in a vertical direction. that is, at the etchingcone angle of 0 degrees. Further, the device isolation trenches 11TI₁ to11TI₃ may be formed in a wedge shape by growing crystal surfaces asdescribed later with reference to FIGS. 6A and 6B.

Next, as illustrated in FIG. 1I, the SiGe mixed crystal layers 11SG₁ to11SG₃ are selectively removed from the silicon epitaxial layers 11ES₁ to11ES₃ above the SiGe mixed crystal layers 11SG₁ to 11SG₃ or from thesubstrate 11 beneath the SiGe mixed crystal layers 11SG₁ to 11SG₃ by dryetching utilizing a mixed gas of hydrogen chloride (HCl) and hydrogen(H₂). Such dry etching may be performed for 120 sec under a noble gas(e.g., Ar) plasma at a pressure of 50 Pa and a temperature of 750° C.while supplying the HCl gas at a flow rate of 1 slm and the H₂ gas at aflow rate of 10 slm.

In addition, the SiGe mixed crystal layers 11SG₁ to 11SG₃ may also beselectively etched by utilizing a chlorine (Cl₂) gas. Further, the SiGemixed crystal layers 11SG₁ to 11SG₃ may also be selectively etched bywet etching.

Alternatively, the SiGe mixed crystal layers 11SG₁ to 11SG₃ may beselectively etched by dry etching utilizing a fluorocarbon (CF₄) gas asan etching gas. In this case, desired etching may be performed for 30sec under a noble gas (e.g., Ar) plasma at a pressure of 100 Pa whilesupplying the CF₄ gas at a flow rate of 1 slm.

As a result of selective etching of the SiGe mixed crystal layers 11SG₁to 11SG₃, voids 11V₁ to 11V₃ are formed corresponding to the SiGe mixedcrystal layers 11SG₁ to 11SG₃ in the substrate 11. Note that asillustrated in FIG. 1E, the void 11V₂ is divided into two parts via thedevice isolation trench 11TI₂.

Note that in the process illustrated in FIG. 1I, the device isolationtrenches 11TI₁ to 11TI₃ may not necessarily reach the silicon substrate11. The device isolation trenches 11TI₁ to 11TI₃ may be formed such thatthe SiGe mixed crystal layers 11SG₁ to 11SG₃ are partially exposed.

In the first embodiment, since the side surfaces of the trenches TA₁ toTA₃ are covered with the thin insulating film 11TOx in the process ofFIG. 1D, the SiGe mixed crystal layers 11SG₁ to 11SG₃ will not bebrought into contact with the side surfaces of the trenches TA₁ to TA₃in the process of FIG. 1F. In the process of FIG. 1I, the siliconepitaxial layers 11ES₁ to 11ES₃ are epitaxially bonded with the siliconsubstrate 11 forming the side surfaces of the trenches TA₁, TA₂ and TA₃.That is, the silicon epitaxial layers 11ES₁ to 11ES₃ are directly bondedwith the side surfaces of the trenches TA₁, TA₂ and TA₃ formed of thesilicon substrate 11 in a lattice matched configuration. Accordingly,even if the voids 11V₁ to 11V₃ are formed by etching of the SiGe mixedcrystal layers 11SG₁ to 11SG₃, the silicon epitaxial layers 11ES₁ to11ES₃ will not fall off of the silicon substrate 11 forming the sidesurfaces of the trenches TA₁, TA₂ and TA₃, which may retain a stablestructure of FIG. 1I.

As illustrated in 1J, an embedded insulating film 11I_(F) is depositedon the obtained structure of FIG. 1I to fill the voids 11V₁ to 11V₃ withthe embedded insulating film 11I_(F). The embedded insulating film11I_(F) includes a silicon oxide film or a silicon nitride film as amajor component, and preferable examples of the deposition processinclude the ALD process, the CVD process and a spin-on-dielectric (SOD)process, which exhibit excellent step coverage (i.e., silicon trenchstep coverage). FIG. 1J illustrates an example in which the embeddedinsulating film 11I_(F) having the silicon oxide film as a majorcomponent is deposited by the ALD process such that the voids 11V₁ to11V₃ are filled by the embedded insulating film 11I_(F). The ALD processmay be performed at a temperature range of 300 to 600° C. by utilizingtetradimethylaminosilane (TDMASi) or ozone (O₃) as a raw material gas.Bis (tertiary-butylamino) silane (BTBAS) or oxygen (O₂) may also beutilized as the raw material gas for the ALD process. The embeddedinsulating film 11I_(F) is deposited on an entire surface of theobtained structure of FIG. 1I in a conformal fashion so as tosubstantially fill the voids 11V₁ to 11V₃ with the embedded insulatingfilm 11I_(F). Note that the voids 11V₁ to 11V₃ may not have to becompletely filled with the embedded insulating film 11I_(F), and thevoids 11V₁ to 11V₃ filled with the embedded insulating film 11I_(F) mayhave unfilled parts (i.e., spaces). If the voids 11V₁ to 11V₃ filledwith the embedded insulating film 11I_(F) have unfilled spaces, apreferable effect of lowering the relative dielectric constant of theentire embedded insulating film 11I_(F) may be obtained.

Further, in the process of FIG. 1J, the embedded insulating film 11I_(F)may be deposited by a combination of the ALD process and the CVD processor a combination of the ALD process and the SOD process. Note that theembedded insulating film 11I_(F) filling the voids 11V₁ to 11V₃ mayinclude spaces. If it is preferable that the embedded insulating film11I_(F) filling the voids 11V₁ to 11V₃ include spaces, the embeddedinsulating film 11I_(F) may be deposited by the CVD process or the SODprocess.

As illustrated in FIG. 1K, the embedded insulating film 11I_(F)deposited in the process of FIG. 1J is removed from the surface of thesilicon substrate 11 by, for example, a wet process utilizing afluorinated acid. Further, as illustrated in FIG. 1L, the deviceisolation trenches 11TI₁ to 11TI₃ are filled with a silicon oxide filmby a plasma enhanced chemical vapor deposition (PECVD) process.Thereafter, the silicon oxide film deposited on the silicon substrate 11is removed by a chemical mechanical polishing (CMP) process, and thedevice isolation trenches 11TI₁ to 11TI₃ are filled with deviceisolation insulating films 11I₁ to 11I₃, thereby forming ashallow-trench isolation (STI) structure.

Accordingly, the device region 11A of the p-channel MOS transistor andthe device region 11B of the n-channel MOS transistor that are formed onthe silicon substrate 11 are defined by the device isolation insulatingfilms 11I₁ to 11I₃ that are formed corresponding to the device isolationregions.

As illustrated in FIG. 1A, the well implantation or the channelimplantation to form the n-well 11NW and the p-well 11PW may beperformed after the device isolation insulating films 11I₄ to 11I₃ areformed.

Further, in the process of FIG. 1L, a thin insulating film 12, whichwill form a gate insulating film of the p-channel MOS transistor or then-channel MOS transistor, is formed on the silicon substrate 11. Thegate insulating film 12 may be formed by subjecting the surface of thesilicon substrate 11 to dry oxidation at approximately 900° C. to form abase oxide film having a film thickness of approximately 1 nm, andsubsequently subjecting the obtained surface of the silicon substrate 11to plasma nitridation under a nitric oxide (NO) gas to convert thesurface of the silicon substrate 11 into an oxynitride film. In thiscase, the plasma nitridation may be performed under a nitrous oxide(N₂O) gas or an ammonia (NH₃) gas other than the NO gas. Further, thegate insulating film 12 may not be limited to the oxynitride film butmay be a high-k dielectric insulating film such as a hafnium oxide(HfO₂) film or a hafnium silicate (HfSiO₄) film. Moreover, gate oxidefilms of different kinds and different film thicknesses may be formedcorresponding to the device regions 11A and 11B by utilizing a differentresist process for each of the device regions 11A and 11B.

Next, as illustrated in FIG. 1M, a polysilicon film (not illustrated) isdeposited with a film thickness of approximately 100 nm on the obtainedstructure of FIG. 1L, namely, on the gate insulating film 12 at anapproximately 600° C. by a low pressure chemical vapor deposition(LPCVD) process. Further, in the process of FIG. 1M, the polysiliconfilm in the device region 11A is covered with a resist pattern and thepolysilicon film in the device region 11B is n-type doped by doping ann-type dopant into the polysilicon film in the device region 11B. Forexample, P (phosphorus) may be doped at an accelerating energy of 30 keVor lower at a dose range of 2×10¹⁵ to 2×10¹⁶ cm⁻² or preferably at anaccelerating energy of 20 keV at a dose of 5×10¹⁵ cm⁻². The ions may beimplanted at any tilt and in one or more incident directions (directionsof twist), and examples of the ions to be implanted may be one or moretypes of ions such as P and As. Note that germanium (Ge) or silicon (Si)may be implanted for pre-amorphization prior to implantation of thedopant. Thereafter, the resist pattern is removed by the ashing processor the wet process utilizing the SPM or the like.

Further, in the process of FIG. 1M, the polysilicon film in the deviceregion 11B is covered with a resist pattern and the polysilicon film inthe device region 11A is p-type doped by doping a p-type dopant into thepolysilicon film in the device region 11A. For example, B (boron) may bedoped at an accelerating energy of 7 keV or lower at a dose range of2×10¹⁵ to 2×10¹⁶ cm⁻², or preferably at an accelerating energy of 5 keVat a dose of 5×10¹⁵ cm⁻². The ions may be implanted at any tilt and inone or more incident directions (directions of twist). Further, examplesof the ions to be implanted may be one or more types of other Bmolecular ions such as B, BF₂ and B₁₀Hx. Note that germanium (Ge) orsilicon (Si) may be implanted for pre-amorphization prior toimplantation of the dopant. Thereafter, the resist pattern is removed bythe ashing process or the wet process utilizing the SPM or the like.

In the process of FIG. 1M, the spike annealing may optionally beperformed on the semiconductor substrate under a condition of a heatingtemperature of 1000° C. and processing duration of approximately 5 secfor promoting the diffusion of the n-type dopant and the p-type dopantimplanted into the polysilicon film.

Subsequently, in the process of FIG. 1M, a gate electrode 13G₁ composedof the p-type polysilicon film is formed in the device region 11A and agate electrode 13G₂ composed of the n-type polysilicon film is formed inthe device region 11B.

Note that in the process of FIG. 1M, the gate electrodes 13G₁ and 13G₂may not be composed of the polysilicon film, and the gate electrodes13G₁ and 13G₂ may be composed of an amorphous film. In this case, anamorphous film may be formed instead of the polysilicon film in theinitial stages of the process of FIG. 1M.

Next, as illustrated in FIG. 1N, an insulating film (not illustrated) isdeposited on the silicon substrate 11 by the CVD process or the likesuch that the deposited insulating film conforms shapes of the siliconsubstrate 11 and the gate electrodes 13G₁ and 13G₂. The insulating filmdeposited on the surfaces of the silicon substrate 11 and the gateelectrodes 13G₁ and 13G₂ is then etched back by a reactive ion etching(RIE) process that reacts in an approximately vertical direction towardthe main surface of the silicon substrate 11, thereby forming side wallspacers 13GW₁ and 13GW₂ composed of the insulating film on the sidesurfaces of the corresponding gate electrode patterns 13G₁ and 13G₂. Theabove insulating film may be formed by etching back an oxide film ofapproximately 10 nm by the LPCVD process at a substrate temperature ofapproximately 600° C. utilizing a raw material oftetraethylorthosilicate (TEOS). Further, the side wall spacers 13GW₁ and13GW₂ composed of the insulating film may also be formed by etching backa silicon nitride (SiN) film of approximately 10 nm by the LPCVD processat a substrate temperature of approximately 650° C. utilizing a rawmaterial of dichlorosilane (SiH₂Cl₂).

Note that in the first embodiment, the side wall spacers 13GW₁ and 13GW₂may not necessarily be formed, and the process of forming the side wallfilms and the side wall spacers may be omitted.

Further, in the process of FIG. 1N, subsequent to the formation of theside wall spacers 13GW₁ and 13GW₂, pocket implantation and extensionimplantation are performed on the device region 11B utilizing the gateelectrode pattern 13G₂ and the side wall spacer 13GW₂ as a mask whilethe device region 11A on the silicon substrate 11 is covered withphotoresist. In this case, the side wall spacer 13GW₂ serves as anoffset function for perfoming the pocket implantation and the extensionimplantation in the device region 11B. As a result, as illustrated inFIG. 1N, a p-type pocket implantation region (not illustrated) and ann-type source/drain extension regions 11 c and 11 d are formed on eachside of the polysilicon gate electrode 13G₂ in the substrate part 11CH₂forming the channel.

The pocket implantation in the device region 11B may be performed bydoping B or the like at an accelerating energy of 20 keV or lower at adose of 5×10¹³ cm⁻² or lower, or preferably at an accelerating energy of10 keV at a dose of 3×10¹³ cm⁻². The ions may be implanted at any tiltand in one or more incident directions (directions of twist), andexamples of the ions to be implanted may be one or more types of Bmolecule ions such as B, In, BF₂ and B₁₀Hx.

The source/drain extension regions 11 c and 11 d may be formed in thedevice region 11B by doping As or the like at an accelerating energy of5 keV or lower at a dose range of 2×10¹³ to 2×10¹⁵ cm⁻², or preferablyat an accelerating energy of 3 keV at a dose of 5×10¹⁴ cm⁻². In thiscase, the ions may be implanted at any tilt and in one or more incidentdirections (directions of twist), and examples of the ions to beimplanted may be one or more types of ions such as As, P and Sb. Notethat germanium (Ge) or silicon (Si) may be implanted forpre-amorphization prior to implantation of the dopant.

Note that if the process of forming the side wall spacers 13GW₁ and13GW₂ is omitted from the process of FIG. 1N, doping is performed byutilizing the gate electrode pattern 13G₂ as a mask to form the pocketimplantation region and the source/drain extension regions 11 c and 11d.

Further, in the process of FIG. 1N, an n-type pocket implantation region(not illustrated) and a p-type source/drain extension regions 11 a and11 b are formed in the device region 11A on the silicon substrate 11.

More specifically, while the device region 11B is covered with theresist pattern, the pocket implantation and the extension implantationare performed in the device region 11A by utilizing the gate electrodepattern 13G₁ and the side wall spacer 13GW₁ formed on the gate electrodepattern 13G₁ as a mask. In this case, the side wall spacer 13GW₁ servesas an offset function for performing the pocket implantation and theextension implantation in the device region 11A.

The pocket implantation in the device region 11B may be perfomed bydoping As or the like at an accelerating energy of 100 keV or lower at adose of 5×10¹³ cm⁻² or lower, or preferably at an accelerating energy of70 keV at a dose of 3×10¹³ cm⁻². In this case, the ions may be implantedat any tilt and in one or more incident directions (directions oftwist), and examples of the ions to be implanted may be one or moretypes of ions such as P, As and Sb.

The source/drain extension regions 11 a and 11 b may be formed in thedevice region 11A by doping B or the like at an accelerating energy of 2keV or lower at a dose range of 2×10¹³ to 2×10¹⁵ cm⁻², or preferably atan accelerating energy of 1 keV at a dose of 5×10¹⁴ cm⁻². In this case,the ions may be implanted at any tilt and in one or more incidentdirections (directions of twist), and examples of the ions to beimplanted may be one or more types of ions such as B, BF₂ and B₁₀Hx.Note that germanium (Ge) or silicon (Si) may be implanted forpre-amorphization prior to implantation of the dopant.

In the device region 11A, the pocket impurity element may be implantedat a position deeper than the p-type source/drain extension regions 11 aand 11 b.

Note that if two or more device regions for p-channel MOS transistor andthe N-channel MOS transistor are formed on the silicon substrate 11, thecoping condition (ion implanting condition) for forming the pocketimplantation region and the source/drain extension regions may bechanged corresponding to each of the device regions. In this case, theprocess of forming a resist pattern, the process of subjecting thepocket implantation to the device regions and the source/drain extensionimplantation to the device regions, and the process of removing theresist pattern may be repeated the number of necessary times for each ofthe device regions.

If the formation of the side wall spacer 13GW₁ is omitted (notperformed), the pocket implantation and the extension implantation inthe device region 11A may be performed by utilizing the gate electrodepattern 13G₁ as a mask.

Next, as illustrated in 1O, an insulating film preferably having HFresistance such as a silicon oxynitride (SiON) film or a silicon nitride(SiN) film is formed with a film thickness range of 20 to 40 nm on theentire surface of the silicon substrate 11 at a low temperature ofapproximately 600° C. by the LPCVD process or the like, such that thegate electrode pattern 13G₁ carrying the side wall spacer 13GW₁ and thegate electrode pattern 13G₂ carrying the side wall spacer 13GW₂ arecovered with the insulating film. Further, the thus formed insulatingfilm is then etched back by the RIE process such that a side wallinsulating film 13SW₁ is formed on each side of the gate electrode 13G₁via the side wall spacer 13GW₁, and similarly, a side wall insulatingfilm 13SW₂ is formed on each side of the gate electrode 13G₂ via theside wall spacer 13GW₂.

Next, as illustrated in FIG. 1P, As may be doped at an acceleratingenergy of 40 keV or lower at a dose range of 5×10¹⁴ to 2×10¹⁶ cm⁻², orpreferably at an accelerating energy of 30 keV at a dose of 2×10¹⁵ cm⁻².In this case, the ions may be implanted at any tilt and in one or moreincident directions (directions of twist), and examples of the ions tobe implanted may be one or more types of ions such as As and P. Thus, ann+ source region 11 g and an n+ drain region 11 h are formed on outersides of the respective side wall insulating films 13SW₂ based on thegate electrode G₂ in the device region 11B.

Further, in the process of FIG. 1P, the resist pattern is subsequentlyremoved and the device region 11B is covered with the resist pattern.Then, B may be doped in the device region 11A at an accelerating energyof 7 keV or lower at a dose range of 5×10¹¹ to 2×10¹⁶ cm⁻², orpreferably at an accelerating energy of 5 keV at a dose of 2×10¹⁵ cm⁻².In this case, the ions may be implanted at any tilt and in one or moreincident directions (directions of twist). Further, examples of the ionsto be implanted may be one or more types of other B molecular ions suchas B, BF₂ and B₁₀Hx. Thus, a p+ source region 11 e and a p+ drain region11 f are formed on outer sides of the respective side wall insulatingfilms 13SW₁ based on the gate electrode 13G₁ in the device region 11A.

Further, as illustrated in FIG. 1Q, a salicide (self-aligned silicide)process, in which a metallic film such as nickel (Ni) or cobalt (Co) isdeposited and the obtained metallic film is rapidly heated, is performedon the obtained structure of FIG. 1P. As a result of the salicideprocess, a silicide layer 14S₁ such as NiSi is formed on a surface ofthe p+ source region 11 e, a similar silicide layer 14D₁ is formed on asurface of the p+ drain region 11 f, a similar silicide layer 14S₂ isformed on a surface of the n+ source region 11 g, a similar silicidelayer 14D₂ is formed on a surface of the n+ drain region 11 h, andsimilar silicide layers 14G₁ and 14G₂ are respectively formed on thesurfaces of the polysilicon gate electrodes 13G₁ and 13G₂.

Further, as illustrated in FIG. 1R, an interlayer insulating film 15 isformed by the plasma CVD process utilizing tetraethylorthosilicate(TEOS) as a raw material such that the gate electrode 13G₁ and the sidewall insulating film 13SW₁ are covered with the interlayer insulatingfilm 15 in the device region 11A and the gate electrode 13G₂ and theside wall insulating film 13SW₂ are covered with the interlayerinsulating film 15 in the device region 11B on the obtained structure ofFIG. 1Q. Subsequently, as illustrated in FIG. 1S, via holes 15A to 15Dare formed in the interlayer insulating film 15 such that the silicidelayers 14S₁, 14D₁, 14S₂ and 14D₂ are exposed from the via holes 15A to15D in interlayer insulating film 15.

Further, as illustrated in FIG. 1T, via plugs 16A to 16D composed oftungsten (W) or copper (Cu) are respectively formed in the via holes 15Ato 15D optionally with not illustrated barrier metal films such astantalum nitride (TaN) or titanium nitride (TiN). Subsequently, the viaplugs 16A to 16D (e.g., tungsten) and the barrier metal are polished bychemical mechanical planarization/polishing (CMP) process until asurface of the interlayer insulating film 15 is exposed, and a wirelayer is subsequently formed. As a result, a semiconductor deviceaccording to the first embodiment is fabricated.

As illustrated earlier with reference to FIG. 1I, according to the firstembodiment, since the side surfaces of the trenches TA₁ to TA₃ arecovered with the thin insulating film 11TOx in the process of FIG. 1D,the SiGe mixed crystal layers 11SG₁ to 11SG₃ will not be brought intocontact with the side surfaces of the trenches TA₁ to TA₃ in the processof FIG. 1F. In the process of FIG. 1I, the silicon epitaxial layers11ES₁ to 11ES₃ are epitaxially and directly bonded with the siliconsubstrate 11 forming the side surfaces of the trenches TA₁, TA₂ and TA₃.That is, the silicon epitaxial layers 11ES₁ to 11ES₃ are directly bondedwith the side surfaces of the trenches TA₁, TA₂ and TA₃ formed of thesilicon substrate 11. Accordingly, even if the voids 11V₁ to 11V₃ areformed by etching of the SiGe mixed crystal layers 11SG₁ to 11SG₃, thesilicon epitaxial layers 11ES₁ to 11ES₃ will not falloff of the sidesurfaces of the trenches TA₁, TA₂ and TA₃, which may retain a stablestructure of FIG. 1I.

Further, according to the first embodiment, the gate insulating films 12and the gate electrodes 13G₁ and 13G₂ are formed on the flat surface ofthe bulk silicon substrate 11 having no treatment such as etching in thep-channel MOS transistor or the n-channel MOS transistor having theembedded insulating film 11I_(F) locally formed beneath the p+ sourceregion 11 e or 11 g and the p+ drain region 11 f or 11 h. Accordingly,the channel regions immediately beneath the gate electrodes may be flatand no defects may be induced in the channel regions. That is, accordingto the first embodiment, the bulk silicon substrate 11 having initialexcellent crystalline quality may be utilized as the channel regions,operation properties of the MOS transistors may be improved, andvariability in the properties may be reduced.

Note that in the first embodiment, a silicon epitaxial layer doped withB at a concentration of 1×10¹⁸ cm-3 or more may be utilized in place ofthe SiGe mixed crystal layers 11SG₁ to 11SG₃.

In addition, in the first embodiment, silicon nitride (SiN) filmpatternd or silicon oxynitride (SiON) film patternd may be utilized inplace of the silicon oxide film patterns 11Ox₁ and 11Ox₂.

Note that in the first embodiment, the process of FIG. 1C may bemodified, and the insulating film 11TOx may be composed of athermally-oxidized film as illustrated in FIG. 2A. Specifically, in thefirst embodiment, since a source extension region and a drain extensionregion are not formed in the substrate parts 11CH₁ and 11CH₂, athermal-oxidizing process may be carried out in the oxygen atmospherewithout allowing the properties of the transistors to be deteriorated.

When the process of FIG. 2A is performed, the thermally-oxidized film11TOx may be removed from the bottom surfaces of the trenches TA₁ to TA₃by anisotropic etching in a similar manner as the preceding process ofFIG. 1D as illustrated in FIG. 2B.

Thereafter, processes similar to those illustrated subsequent to FIG. 1Emay be carried out to fabricate a semiconductor device having astructure substantially identical to that illustrated in FIG. 1T. Notethat in this case, the thermally-oxidized film 11TOx is utilized inplace of the insulating film 11TOx.

Note that in the structure of FIG. 1S, the embedded insulating film11I_(F) is formed adjacent to the insulating film 11TOx. Accordingly, ifthe embedded insulating film 11I_(F) and the insulating film 11TOx areboth formed of a silicon oxide film, it may be slightly difficult todiscriminate the embedded insulating film 11I_(F) from the insulatingfilm 11TOx. However, as illustrated in FIG. 1F, the upper end of thesilicon oxide film 11TOx is formed at the position slightly lower thanthe position of the upper end of the embedded insulating film 11I_(F)replacing the SiGe mixed crystal layer 11SG₁. Thus, the upper end of thesilicon oxide film 11TOx forms a recess configuration. Hence, it may bepossible to discriminate the embedded insulating film 11I_(F) from theinsulating film 11TOx. Further, if the insulating film 11TOx is formedof the thermally-oxidized film, the amount of the dopant may be small.Accordingly, it may be possible to discriminate the insulating film11TOx from the embedded insulating film 11I_(F) formed by the vaporphase deposition process.

Second Embodiment

Next, a method for fabricating a MOS transistor according a secondembodiment is described with reference to FIGS. 3A to 3X.

As illustrated in FIG. 3A, in the second embodiment, initially, deviceisolation regions 31I₁ to 31I₃ having shallow trench isolation (STI)structure are formed such that a device region 31A of the p-channel MOStransistor and a device region 31B of the n-channel MOS transistor,which are to be formed on a silicon substrate 31 composed of singlecrystal bulk silicon, are mutually isolated from each other via thedevice isolation regions 31I₁ to 31I₃. Accordingly, the device region31A and the device region 31B are defined via the device isolationregions 31I₁ to 31I₃.

Next, as illustrated in FIG. 3B, while the device region 31A isprotected (covered) with a not illustrated resist pattern, a p-well 11PWis formed by doping boron (B) or the like in the device region 31B at anaccelerating energy of 300 keV or lower at a dose of 5×10¹³ cm⁻² orlower, or preferably at an accelerating energy of 150 keV at a dose of3×10¹³ cm⁻². The ions may be implanted at any tilt and in one or moreincident directions (directions of twist), and examples of the ions tobe implanted may be one or more types of ions such as BF₂ and In otherthan B.

In this case, B (boron) may be doped in the device region 31B of thesilicon substrate 31 at an accelerating energy of 150 keV or lower at adose of 1×10¹³ cm⁻² or lower, or preferably at an accelerating energy of30 keV at a dose of 5×10¹² cm⁻² so as to perform channel stopimplantation. The ions may be implanted to perform the channel stopimplantation at any tilt and in one or more incident directions(directions of twist), and examples of the ions to be implanted may beone or more types of ions such as BF₂ and In other than B.

Next, ions are implanted for adjusting a threshold of the n-channel MOStransistor. For example, B may be doped at an accelerating energy of 40keV or lower at a dose of 3×10¹³ cm⁻² or lower, or preferably at anaccelerating energy of 20 keV at a dose of 1×10¹³ cm⁻². In this case,the ions may be implanted at any tilt and in one or more incidentdirections (directions of twist). Further, examples of the ions to beimplanted may be one or more types of other B molecular ions such as In,BF₂ and B₁₀Hx other than B.

Next, as illustrated in FIG. 3B, after the resist pattern is removedfrom the device region 31A and the device region 31B is protected(covered) with a not illustrated resist pattern (differing from the oneremoved from the device region 31A), an n-well 11NW is formed by dopingphosphorus (P) or the like as an impurity element in the device region31A at an accelerating energy of 600 keV or lower at a dose of 5×10¹³cm⁻² or lower, or preferably at an accelerating energy of 350 keV at adose of 3×10¹³ cm⁻². The ions may be implanted at any tilt and in one ormore incident directions (directions of twist), and examples of the ionsto be implanted may be one or more types of ions such as arsenic (As)and antimony (Sb) other than P.

In this case, As may be doped in the device region 31A of the siliconsubstrate 31 at an accelerating energy of 300 keV or lower at a dose of1×10¹³ cm⁻² or lower, or preferably at an accelerating energy of 100 keVat a dose of 5×10¹² cm⁻² so as to perform channel stop implantation. Theions may be implanted at any tilt and in one or more incident directions(directions of twist), and examples of the ions to be implanted may beone or more types of ions such as As and Sb other than P.

Next, ions are implanted for adjusting a threshold of the p-channel MOStransistor. For example, As may be doped at an accelerating energy of200 keV or lower at a dose of 3×10¹³ cm⁻² or lower, or preferably at anaccelerating energy of 130 keV at a dose of 3×10¹³ cm⁻². The ions may beimplanted at any tilt and in one or more incident directions (directionsof twist), and examples of the ions to be implanted may be one or moretypes of ions such as P, As and Sb.

Further, in the process of FIG. 3B, the resist pattern covering thedevice region 31B is subsequently removed by an asking process or a wetprocess utilizing a sulfuric acid hydrogen peroxide mixture (SPM) or thelike. Thereafter, the silicon substrate 31 is spike annealed at 1000° C.for approximately 10 sec to activate the impurity element such as B, Por As doped in the silicon substrate 31.

Next, as illustrated in FIG. 3C, an oxide film is formed with a filmthickness of approximately 1 nm on the silicon substrate 31 by dryoxidation at a substrate temperature of approximately 900° C., and theobtained oxide film is then subject to plasma nitridation under a nitricoxide (NO) gas. As a result, oxynitride films (i.e., gate insulatingfilms) 32, which will form a gate insulating film of the p-channel MOStransistor and the n-channel MOS transistor, are formed on a surface ofthe silicon substrate 31. Note that the plasma nitridation to form theoxynitride films (i.e., gate insulating films) 32 may be performed undera nitrous oxide (N₂O) gas or an ammonia (NH₃) gas other than the NO gas.

Further, in the second embodiment, the gate insulating films of thep-channel MOS transistor and the n-channel MOS transistor may not belimited to the oxynitride film but may be a high-k dielectric insulatingfilm such as a hafnium oxide (HfO₂) film or a hafnium silicate (HfSiO₄)film. Further, the gate insulating films of different kinds or differentfilm thicknesses may be formed corresponding to the device regions 31Aand 31B by utilizing a different resist process for each of the deviceregions 31A and 31B.

Next, in FIG. 3C, a not illustrated polysilicon film is deposited with afilm thickness of approximately 100 nm on the insulating film, whichwill form the gate insulating films of the thus formed p-channel MOStransistor and n-channel MOS transistor, at a substrate temperature ofapproximately 600° C. by a low pressure chemical vapor deposition(LPCVD) process. Further, while forming a resist pattern on thepolysilicon film in the device region 31A to cover the device region31A, the polysilicon film in the device region 31B is n-type doped bydoping an n-type dopant into the polysilicon film in the device region11B. For example, P (phosphorus) may be doped at an accelerating energyof 30 keV or lower at a dose range of 2×10²⁵ to 2×10²⁶ cm⁻², orpreferably at an accelerating energy of 20 keV at a dose of 5×10²⁵ cm⁻².The ions may be implanted at any tilt and in one or more incidentdirections (directions of twist), and examples of the ions to beimplanted may be one or more types of ions such as P and As. Note thatgermanium (Ge) or silicon (Si) may be implanted for pre-amorphizationprior to implantation of the dopant. Thereafter, the resist pattern,which is formed on the polysilicon film to cover (protect) the deviceregion 31A, is removed.

Subsequently, in the process of FIG. 3C, a resist pattern for coveringthe device region 31B is formed on the polysilicon film formed in thedevice region 31B, and the polysilicon film formed in the device region31A is p-type doped by doping a p-type dopant into the polysilicon filmin the device region 31A. For example, B (boron) may be doped at anaccelerating energy of 7 keV or lower at a dose range of 2×10¹⁵ to2×10¹⁶ cm⁻², or preferably at an accelerating energy of 5 keV at a doseof 5×10¹⁵ cm⁻². The ions may be implanted at any tilt and in one or moreincident directions (directions of twist). Further, examples of the ionsto be implanted may be one or more types of other B molecular ions suchas B, BF₂ and B₁₀Hx. Note that germanium (Ge) or silicon (Si) may beimplanted for pre-amorphization prior to implantation of the dopant.Further, the resist pattern is removed from the polysilicon film formedin the device retion 31B by the asking process or the wet processutilizing the SPM or the like.

MOreover, the spike annealing may optionally be performed on the siliconsubstrate 31 under a condition of a heating temperature of 1000° C. andprocessing duration of approximately 5 sec for promoting the diffusionof the n-type dopant and the p-type dopant implanted into thepolysilicon film.

Further, in the process of FIG. 3C, the polysilicon film is patterned byanisotropic etching, such that a gate electrode pattern 33G₁ is formedon the silicon substrate 31 via the gate insulating film 32 in thedevice region 31A and a gate electrode pattern 33G₂ is formed on thesilicon substrate 31 via the gate insulating film 32 in the deviceregion 31B.

Note that in the process of FIG. 3C, an amorphous silicon film may beformed in place of the polysilicon film. In this case, the gateelectrodes 31G₁ and 32G₂ may be formed of the amorphous silicon film.

Next, as illustrated in FIG. 3D, a side wall spacer 33GW₁ is formed oneach side of the gate electrode 31G₁ and a side wall spacer 33GW₂ isformed on each side of the gate electrode 33G₂, in a similar manner asthe formation of the side wall spacers 13GW₁ and 13GW₂ in the firstembodiment. Further, while the device region 31A of the siliconsubstrate 31 is protected (covered) with photoresist, pocketimplantation and extension implantation are performed on the deviceregion 31B utilizing the gate electrode pattern 33G₂ and the side wallspacer 33GW₂ as a mask. As a result, a p-type pocket implantation region(not illustrated) and an n-type source/drain extension regions 31 c and31 d are formed in a similar manner as the formation of the p-typepocket implantation region and the n-type source/drain extension regions11 c and 11 d in the first embodiment.

Further, in the process of FIG. 3D, an n-type pocket implantation region(not illustrated) and a p-type source/drain extension regions 31 a and31 b are formed in the device region 31A of the silicon substrate 31, ina similar manner as the formation of the n-type pocket implantationregion and the p-type source/drain extension regions 11 a and 11 b inthe first embodiment.

Next, as illustrated in FIG. 3E, side wall insulating films 33SW₁ and33SW₂ are formed on the gate electrodes 33G₁ and 33G₂ via thecorresponding side wall spacers 33GW₁ and 33GW₂, in a similar manner asthe formation of the side wall insulating films 13SW₁ and 13SW₂ in thefirst embodiment.

Further, in the process of FIG. 3E, dry etching is performed utilizingthe side wall insulating films 33SW₁ and 33SW₂ as a mask and Cl₂ and HCLas an etching gas, in a similar manner as the process of FIG. 10 in thefirst embodiment. As a result, the device region 31A of the siliconsubstrate 31 is covered with the gate electrode pattern 33G₁ and theside wall insulating film 33GW₁, and trenches 31TA₁ and 31TA₂ are formedwith a depth range of 40 to 150 nm on outer sides of a substrate part31CH₁ including a channel region in which a p-channel transistor will beformed. Likewise, in the process of FIG. 3E, the device region 31B ofthe silicon substrate 31 is covered with the gate electrode pattern 33G₂and the side wall insulating film 33GW₂, and trenches 31TA₃ and 31TA₄are formed with a depth range of 40 to 150 nm on outer sides of asubstrate part 31CH₂ including a channel region in which an n-channeltransistor will be formed.

Note that in the process of FIG. 3E, though not illustrated, maskpatterns similar to the side wall insulating films 33SW₁ and 33SW₂ areformed on the gate electrode patterns 33G₁ and 33G₂ so that the gateelectrode patterns 33G₁ and 33G₂ are prevented from being etched whenthe trenches 31TA₁ and 31TA₂ are formed. Such mask patterns formed onthe gate electrode patterns 33G₁ and 33G₂ are removed in thelater-described process, for example, of FIG. 3P.

Next, as illustrated in FIG. 3F, an insulating film 31TOx such as asilicon oxide film, a silicon nitride film or a silicon oxynitride(SiON) film is deposited on the structure obtained in the process ofFIG. 3E with a film thickness less than the film thickness of the gateside wall insulating films 33SW₁ and 33SW₂, or preferably with a filmthickness of 10 nm or less, by a low temperature chemical vapordeposition (CVD) process performed at 400° C. or lower, such as theplasma CVD process or the ALD process. As a result, side surfaces andbottom surfaces of the trenches 31TA₁ to 31TA₄ are uniformly coveredwith the insulating film 31TOx. The concentration profile of theimpurity element (dopant) may not be changed in the source extensionregion 31 a and the drain extension region 31 b formed in the substratepart 31CH₁, or in the source extension region 31 c and the drainextension region 31 d formed in the substrate part 31CH₂ by performingthe deposition of the insulating film 31TOx at the low temperature. Notethat it is preferable that the insulating film 31TOx have a filmthickness of 2 nm or more.

Next, as illustrated in FIG. 3G, parts of the insulating film 31TOxcovering the bottom surfaces of the trenches 31TA₁ to 31TA₄ are removedby anisotropic etching that reacts approximately perpendicular to thesurface of the silicon substrate 31. As a result, the silicon substrate31 is exposed from the bottom surfaces of the trenches 31TA₁ to 31TA₄.

If the insulating film 31TOx is formed of the same material as the sidewall insulating films 33SW₁ and 33SW₂ of the gate electrodes 33G₁ and33G₂, the side wall insulating films 33SW₁ and 33SW₂ may be etchedsimultaneously with the parts of the insulating film 31TOx by theanisotropic etching. However, since the film thicknesses of the sidewall insulating films 33SW₁ and 33SW₂ are far thicker than that of theinsulating film 31TOx, the side wall insulating films 33SW₁ and 33SW₂will not be removed completely.

Next, as illustrated in FIG. 3H, the SiGe mixed crystal layers 31SG₁,31SG₂, 31SG₃ and 31SG₄ epitaxially grow in the trenches 31TA₁ to 31TA₄illustrated in FIG. 3G by utilizing a selective epitaxial growthtechnology in a similar manner as the epitaxial growth in the firstembodiment, thereby filling lower parts of the trenches 31TA₁ to 31TA₄.

Next, as illustrated in FIG. 3I, parts of the insulating film 31TOxexposed from the side surfaces of the trenches 31TA₁ to 31TA₄ areremoved by dry etching or wet etching. As a result, the siliconsubstrate 31 is exposed from the side surfaces of the trenches 31TA₁ to31TA₄. If the insulating film 31TOx is formed of the same material asthe side wall insulating films 33SW₁ and 33SW₂ of the gate electrodes33G₁ and 33G₂, the side wall insulating films 33SW₁ and 33SW₂ may beetched simultaneously with the parts of the insulating film 31TOx by thedry etching or wet etching. However, since the film thicknesses of theside wall insulating films 33SW₁ and 33SW₂ are far thicker than that ofthe insulating film 31TOx, the film thicknesses of the side wallinsulating films 33SW₁ and 33SW₂ will not be decreased substantially, orthe side wall insulating films 33SW₁ and 33SW₂ will not be removedcompletely.

Next, as illustrated in FIG. 3J, in the trenches 31TA₁ to 31TA₄, siliconepitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ are epitaxially formed onthe SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ such thatthe trenches 31TA₁ to 31TA₄ are completely filled with the siliconepitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ and the SiGe mixedcrystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄.

For example, the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄are deposited with a film thickness range of 20 to 80 nm by the CVDprocess using a mixed gas of dichlorosilane, monogermane, hydrogenchloride and hydrogen, under a similar condition as the firstembodiment. The silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄are subsequently deposited with a thickness range of 20 to 70 nm on theSiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ by the CVDprocess using a mixed gas of dichlorosilane, hydrogen chloride andhydrogen, also under a similar condition as the first embodiment.

In the second embodiment, as illustrated in the process of FIG. 3H, theside surfaces of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and31SG₄ are covered with the insulating film 31TOx when growing the SiGemixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ in the trenches 31TA₁to 31TA₄. Accordingly, the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃and 31SG₄ will not grow on the side surfaces of the trenches 31TA₁ to31TA₄. Further, when the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃and 31ES₄ are subsequently formed on the SiGe mixed crystal layers31SG₁, 31SG₂, 31SG₃ and 31SG₄ in the trenches 31TA₁ to 31TA₄, thesilicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ may securelylattice match the silicon substrate 31 that forms the substrate parts31CH₁ and 31CH₂ in the side surfaces of the trenches 31TA₁ to 31TA₄.

Next, as illustrated in FIG. 3K, device isolation films forming thedevice isolation structures 31I₁ to 31I₃ are depressed by wet etchingutilizing fluorinated acid or by dry etching of the silicon oxide film.As a result, the side surfaces of the SiGe mixed crystal layers 31SG₁,31SG₂, 31SG₃ and 31SG₄ are exposed.

Note that in the process of FIG. 3K, the device isolation films formingthe device isolation structures 31I₁ to 31I₃ may be depressed inadvance, and then the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and31SG₄, and the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄may epitaxially grow thereafter.

Note that in the structure obtained in the process of FIG. 3K, the sidesurfaces of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄,or the side surfaces of the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃and 31ES₄ may be formed of a single crystalline plane or pluralcrystalline planes.

Next, as illustrated in FIG. 3L, the SiGe mixed crystal layers 31SG₁,31SG₂, 31SG₃ and 31SG₄ are selectively etched from the silicon substrate31 and the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ by dryetching utilizing a mixed gas of chlorine (Cl₂) and hydrogen, orutilizing a hydrogen chloride gas, by wet etching utilizing a mixedsolution of fluorinated acid, nitric acid, acetic acid and the like, orby dry etching utilizing a tetrafluoromethane (CF₄) gas diluted by argon(Ar), such that voids 31V₁ to 31V₄ are formed in regions correspondingto the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ of thesilicon substrate 31 in a similar manner as in the first embodiment.

Note that in the process of FIG. 3L, as described earlier, the siliconepitaxial layers 31ES₁ and 31ES₂ epitaxially lattice match the substratepart 31CH₁, and the silicon epitaxial layers 31ES₃ and 31ES₄ epitaxiallylattice match the substrate part 31CH₂. Accordingly, even if the SiGemixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ are selectivelyremoved from the substrate parts 31CH₁ and 31CH₂, and the siliconepitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄, the silicon epitaxiallayers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ will not fall off of the substrateparts 31CH₁ or 31CH₂ of the silicon substrate 31.

Further, if the etching process in FIG. 3L is performed by the dryetching, the process of depressing the device isolation structures 31I₁to 31I₃ by etching illustrated in FIG. 3K may be performed before thedeposition of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and31SG₄ and the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄. Inthis manner, even if the process of depressing the device isolationstructures 31I₁ to 31I₃ is performed by wet etching, the depositionprocess of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄,the deposition process of the silicon epitaxial layers 31ES₁, 31ES₂,31ES₃ and 31ES₄, and the selective etching process of FIG. 3L may becontinuously performed in the same process device without having totemporarily remove the treating substrate from the process device in themiddle of the above processes.

In the second embodiment, the SiGe mixed crystal layers 31SG₁ to 31SG₄may include the atomic fraction of Ge of approximately 20% similar tothe first embodiment. However, a large amount of Ge may be contained inthe SiGe mixed crystal layers 31SG₁ to 31SG₄ within a range of allowingthe SiGe mixed crystal layers 31SG₁ to 31SG₄ to epitaxially grow on thesurface of the silicon substrate 31, such as the SiGe mixed crystallayers 31SG₁ to 31SG₄ having the atomic fraction of Ge of approximately40%. Since the such as the SiGe mixed crystal layers 315G₁ to 315G₄include a high concentration of Ge, the selectivity in the etchingprocess of FIG. 3L may be improved. Further, SiGeC mixed crystal mayoptionally be utilized as the SiGe mixed crystal layers 31SG₁ to 31SG₄.

Next, as illustrated in FIG. 3M, an embedded insulating film 31I_(F)formed of a silicon oxide film or a silicon nitride film as a majorcomponent is deposited on the structure obtained in thr process of FIG.3L by a deposition process exhibiting excellent step coverage, such asthe ALD process, the CVD process, or the SOG process, such that thevoids 31V₁ to 31V₄ are filled with the embedded insulating film 31I_(F).In the example of FIG. 3M, the embedded insulating film 31I_(F) isdeposited by the ALD process. In this deposition condition, the ALDprocess is performed at a temperature range of 300 to 600° C. byutilizing tetradimethylaminosilane (TDMASi) or ozone (O₃) as a rawmaterial gas. Alternatively, bis(tertiary-butylamino) silane (BTBAS) oroxygen (O₂) may also be utilized as the raw material gas for the ALDprocess. Note that in the second embodiment, the voids 31V₁ to 31V₄ maynot have to be completely filled with the embedded insulating film31I_(F), and the voids 31V₁ to 31V₄ filled with the embedded insulatingfilm 31I_(F) may partially have unfilled parts (i.e., spaces).

Next, as illustrated in FIG. 3N, wet etching or dry etching is performedon the structure obtained in FIG. 3M, such that the embedded insulatingfilm 31I_(F) is removed from the surfaces of the silicon epitaxiallayers 31ES₁ to 31ES₄, the surfaces of the side wall insulating films33SW₁ and 33SW₂, and the exposed surfaces of the gate electrodes 33G₁and 33G₂. As a result of the above etching process of FIG. 3M, trenches31TI₁ to 31TI₃ corresponding to the initial device isolation trenchesmay be formed corresponding to the device isolation structures 31I₁ to31I₃ on the side surfaces of the silicon epitaxial layers 31ES₁ to31ES₄.

Further, in the process of FIG. 3N, the side wall insulating films 33SW₁and 33SW₂ are depressed by the preceding etching process of FIG. 3L.Accordingly, the side wall insulating films 33SW₁ and 33SW₂ are onceremoved, and new side wall insulating films are formed on the sidesurfaces of the gate electrodes 33G₁ and 33G₂ in the process of FIG. 3O.

More specifically, as illustrated in FIG. 3P, an insulating film 34,such as a silicon oxide film, a silicon nitride film, or a layered filmcomposed of the silicon oxide film and the silicon nitride film, isdeposited on the obtained structure of FIG. 3O by the CVD process, suchthat the insulating film 34 matches the base structure. Thereafter, theinsulating film 34 is etched back in the process illustrated in FIG. 3Q.As a result, a new side wall insulating film 33SW₃ is formed on each ofthe side surfaces of the gate electrode 33G₁ and similarly, a new sidewall insulating film 33SW₄ is formed on each of the side surfaces of thegate electrode 33G₂ (see FIG. 34). Note that as illustrated in FIG. 3Q,the insulating film 34 remaines on the side surfaces of the trenches31I₁ to 31I₃.

Next, as illustrated in FIG. 3R, while the device region 31A illustratedin FIG. 3Q is covered (protected) with a resist pattern R31, an n-typeimpurity element such as As may be doped in the device region 31B byutilizing the gate electrode 33G₂ and the side wall insulating film33SW₄ as a mask at an accelerating energy of 40 keV or lower at a doserange of 5×10¹⁴ to 2×10¹⁶ cm⁻², or preferably at an accelerating energyof 30 keV at a dose of 2×10¹⁵ cm⁻². In this case, the ions may beimplanted at any tilt and in one or more incident directions (directionsof twist), and examples of the ions to be implanted may be one or moretypes of ions such as As and P. As a result, an n-type source region 31g and an n-type drain region 31 h are formed in the silicon epitaxiallayers 31ES₃ and 31ES₄ at positions deeper than the positions of thesource extension region 31 c and the drain extension region 31 dpreviously formed in the substrate part 31CH₂ (see FIG. 3S).

As illustrated in FIG. 3S, while the resist pattern R31 is removed fromthe device region 31A, the device region 31B illustrated in FIG. 3Q isnewly covered (protected) with a resist pattern R32. Further, a p-typeimpurity element such as B may be doped by utilizing the gate electrode33G₁ and the side wall insulating film 33SW₃ as a mask at anaccelerating energy of 7 keV or lower at a dose range of 5×10²⁴ to2×10²⁶ cm⁻², or preferably at an accelerating energy of 5 keV at a doseof 2×10²⁵ cm⁻². In this case, the ions may be implanted at any tilt andin one or more incident directions (directions of twist). Further,examples of the ions to be implanted may be one or more types of other Bmolecular ions such as B, BF₂ and B₁₀Hx. As a result, a p-type sourceregion 31 e and a p-type drain region 31 f are formed in the siliconepitaxial layers 31ES₁ and 31ES₂ at positions deeper than the positionsof the source extension region 31 a and the drain extension region 31 bpreviously formed in the substrate part 31CH₁.

As illustrated in FIG. 3T, low-resistance silicide layers 36 a, 36 b, 36c, 36 d, 36 e and 36 f such as NiSi are formed on the exposed surfacesof the silicon epitaxial layers 31ES₁ to 31ES₄, and the exposed surfacesof the polysilicon gate electrodes 33G₁ and 33G₂ by a salicide process,or the like.

Alternatively, after the process of 3Q, the remaining insulating film 34may be removed from the trenches 31TI₁ to 31TI₃ by wet etching utilizingHF, and the silicide layers may be formed on the obtained structure. Asa result, the structure illustrated in FIG. 3U may be obtained. In thestructure of FIG. 3U, the silicide layers 36 a to 36 d are formed suchthat the silicide layers 36 a to 36 d respectively cover the sidesurfaces of the trenches 31TI₁ to 31TI₃.

Further, as illustrated in FIG. 3V, an interlayer insulating film 37 isfilled in the trenches 31TI₁ to 31TI₃ in a similar manner as the processof FIG. 1R. Subsequently, as illustrated in FIG. 3W, via holes 37A to37D are formed in the interlayer insulating film 37 such that thesilicide layers 36 a to 36 d that cover the p-type source region 31 e,the p-type drain region 31 f, the n-type source region 31 g and then-type drain region 31 h are exposed from the interlayer insulating film37.

Further, as illustrated in FIG. 3X, via plugs 38A to 38D arerespectively formed in the via holes 37A to 37D, such that the via plugs38A to 38D are brought into contact with the silicide layers 36 a to 36d.

As illustrated earlier with reference to FIG. 3L, according to thesecond embodiment, since the side surfaces of the trenches 31TA₁ to31TA₃ are covered with the thin insulating film 31TOx in the process ofFIG. 3F, the SiGe mixed crystal layers will not be brought into contactwith the side surfaces of the trenches 31TA₁ to 31TA₃ in the process ofFIG. 3H. In the process of FIG. 3J, the silicon epitaxial layers 31ES₁to 31ES₄ are epitaxially and directly bonded with the silicon substrate31 forming the side surfaces of the trenches 31TA₁ to 31TA₄. That is,the silicon epitaxial layers 31ES₁ to 31ES₄ are directly bonded with theside surfaces of the trenches 31TA₁ to 31TA₄ formed of the siliconsubstrate 31. Accordingly, even if the voids 31V₁ to 31V₄ are formed byetching of the SiGe mixed crystal layers 31SG₁ to 31SG₄, the siliconepitaxial layers 31ES₁ to 31ES₄ will not fall off of the side surfacesof the trenches 31TA₁ to 31TA₄, which may retain a stable structure ofFIG. 3L.

Further, according to the second embodiment, the gate insulating films32 and the gate electrodes 33G₁ and 33G₂ are formed on the surface ofthe bulk silicon substrate 31 having no treatment, such as etching, inthe p-channel MOS transistor or the n-channel MOS transistor having theembedded insulating film 31I_(F) locally formed beneath the sourceregion 31 e or 31 g and the drain region 31 f or 31 h. Accordingly, thechannel regions immediately beneath the gate electrodes may be flat andno defects may be induced in the channel regions. That is, according tothe second embodiment, since the bulk silicon substrate 31 havinginitial excellent crystalline quality may be utilized as the channelregions, operation properties of the MOS transistors may be improved andvariability in the properties may be reduced.

Third Embodiment

FIGS. 4A to 4C are diagrams illustrating fabrication processes of asemiconductor device according to a third embodiment subsequent to theprocess of FIG. 3N, which are implemented as a modification of thesecond embodiment. Note that in FIGS. 4A to 4C, processes and componentssimilar to those already described will be provided with the samereference numerals and will not be repeatedly described. FIG. 4Aillustrates components and processes similar to those of FIG. 3N, andtheir descriptions are thus omitted.

In the third embodiment, after the process of FIG. 4A, a subsequentprocess is carried out without removing the side wall insulating films33SW₁ and 33SW₂, which differs from the process of FIG. 3O describedearlier.

That is, in the process of FIG. 4B, the ion implantation correspondingto the process of FIG. 3O is performed by utilizing the gate electrode33G₂ and the side wall insulating film 33SW₂ as a mask, and the ionimplantation corresponding to the process of FIG. 3S is performed byutilizing the gate electrode 33G₁ and the side wall insulating film33SW₁ as a mask. As a result, an n-type source region 31 g and an n-typedrain region 31 h are formed in the silicon epitaxial layers 31ES₃ and31ES₄ and a p-type source region 31 e and a p-type drain region 31 f areformed in the silicon epitaxial layers 31ES₁ and 31ES₂. Note that in theprocess of FIG. 4B, the side wall insulating films 33SW₁ and 33SW₂ aredepressed as a result of the selective etching process of FIG. 3L.Accordingly, the p-type source region 31 e and the p-type drain region31 f extend to respective positions corresponding to outer side surfacesof the side wall insulating films 33SW₁ in the substrate part 31CH₁.Similarly, in the process of FIG. 4B, the n-type source region 31 g andthe n-type drain region 31 h extend to respective positionscorresponding to outer side surfaces of the side wall insulating films33SW₂ in the substrate part 31CH₂.

Further, as illustrated in FIG. 4C, silicide layers 36 a, 36 b, 36 c, 36d, 36 e and 36 f are formed on the exposed silicon surfaces of FIG. 4Bby a salicide process. Specifically, as previously illustrated earlierin FIG. 3U, the silicide layer 36 a is formed on the p-type sourceregion 31 e, the silicide layer 36 b is formed on the p-type drainregion 31 f, the silicide layer 36 c is formed on the n-type sourceregion 31 g, the silicide layer 36 d is formed on the n-type drainregion 31 h, the silicide layer 36 e is formed on a top surface of thepolysilicon gate electrode 33G₁, and the silicide layer 36 f is formedon a top surface of the polysilicon gate electrode 33G₂.

After the process of FIG. 4C, a semiconductor device having a structuresimilar to that illustrated in FIG. 3X may be formed on the siliconsubstrate 11 by performing the processes of FIG. 3V or 3Q to 3X. Notethat as illustrated earlier, in the second embodiment, the p-type sourceregion 31 e and the p-type drain region 31 f extend to the respectivepositions corresponding to outer side surfaces of the side wallinsulating films 33SW₁ in the substrate part 31CH₁. Similarly, in theprocess of FIG. 4B, the n-type source region 31 g and the n-type drainregion 31 h extend to the respective positions corresponding to outerside surfaces of the side wall insulating films 33SW₂ in the substratepart 31CH₂.

In the second embodiment, since the side wall insulating films 33SW₁ and33SW₂ are continuously used as the side wall insulating films after theselective etching process of FIG. 3L, the processes of FIGS. 3O to 3Q,and the removing process of the insulating film 34 remaining in thetrenches 31TI₁ to 31TI₃ may not be necessarily carried out, and hencemay be omitted. Accordingly, the fabrication processes of thesemiconductor device may be simplified.

Note the in the above embodiments, subsequent to the process of FIG. 1O,the silicon epitaxial layers 11ES₁ to 11ES₄ may be selectively removedfrom the embedded insulating film 11I_(F) beneath the silicon epitaxiallayers 11ES₁ to 11ES₄ by wet etching or dry etching as illustrated inFIG. 5A. Subsequently, in the process of FIG. 5B, SiGe mixed crystallayers 11SGV₁ and 11SGV₂ may epitaxially grow on the substrate part11CH₁ forming silicon monocrystal such that the SiGe mixed crystallayers 11SGV₁ and 11SGV₂ are filled in the respective trenches in thedevice region 11A, and likewise, SiC mixed crystal layers 11SCV₁ and11SCV₂ may epitaxially grow on the substrate part 11CH₂ forming siliconmonocrystal such that the SiC mixed crystal layers 11SCV₁ and 11SCV₂ arefilled in the respective trenches in the device region 11B. Accordingly,uniaxial compressive stress may be induced in a channel region of thep-channel MOS transistor formed in the device region 11A and uniaxialtensile stress may be induced in a channel region of the n-channel MOStransistor formed in the device region 11B. As a result, the operationalspeeds of the p-channel MOS transistor and the n-channel MOS transistormay be improved.

In this case, as illustrated in FIG. 5C, after the formation of the p+source region 11 e and the p+ drain region 11 f of the p-channel MOStransistor, the n+ source region 11 g and the n+ drain region 11 h ofthe n-channel MOS transistor, and the silicide layers 14S₁, 14D₁, 14S₂,14D₂, 14G₁ and 14G₂, a compressive stress film 17A such as SiN is formedsuch that the compressive stress film 17A covers the gate electrode 13G₁and the side wall insulating film 13SW₁ on the p-channel MOS transistor,and likewise, a compressive stress film 17B such as SiN is formed suchthat the compressive stress film 17B covers the gate electrode 13G₂ andthe side wall insulating film 13SW₂ on the n-channel MOS transistor.With this configuration, the uniaxial compressive stress of thep-channel MOS transistor and the uniaxial tensile stress of then-channel MOS transistor may be increased.

Note that in FIGS. 5A to 5C, processes and components similar to thosealready described will be provided with the same reference numerals andwill not be repeatedly described.

Further, in the structure of FIG. 5A, the side surfaces of the trenchesTA₁ and TA₂ (see FIG. 6A) may be formed in a wedge shape such that theside surfaces of the trenches TA₁ and TA₂ form wedge-shaped recesses inthe substrate parts 11CH₁ and 11CH₂. In this case, as illustrated inFIG. 6B, if the trenches TA₁ and TA₂ are filled with the SiGe mixedcrystal layers 11SGV₁ and 11SGV₂ or the SiC mixed crystal layers 11SCV₁and 11SCV₂ serving as a compressive stress source or a tensile stresssource, points of the wedge shaped side surfaces of the trenches TA₁ andTA₂ interfere with immediate beneath the channel parts of the substrateparts 11CH₁ and 11CH₂. As a result, a large amount of tensile stress maybe applied to the channels.

In this case, the insulating film 11TOx may be initially formed on thewedge shaped side surfaces of the trenches TA₁ and TA₂. Accordingly, themechanically unstable structure may be stabilized when the SiGe mixedcrystal layers 11SG₁ to 11SG₃ are removed in the process similar to theprocess of FIG. 1I prior to filling the embedded insulating film 11I_(F)in the trenches TA₁ and TA₂.

Note that in the example of FIG. 6B, the SiGe mixed crystal layers11SGV₁ and 11SGV₂ and the SiC mixed crystal layers 11SCV₁ and 11SCV₂serving as the stress sources are formed at a position higher than aninterface between the gate insulating film 12 and the silicon substrate11. With this configuration, the source resistance may be reduced.

Fourth Embodiment

Next, a method for fabricating a semiconductor device according a fourthembodiment is described with reference to FIGS. 7A to 7R. Note that inFIGS. 7A to 7R, processes and components similar to those alreadydescribed will be provided with the same reference numerals and will notrepeatedly described.

As illustrated in FIG. 7A, in the fourth embodiment, the gate electrodepattern 33G₁ is formed corresponding to the substrate part 31CH₁ in thedevice region 31A and the gate electrode pattern 33G₂ is formedcorresponding to the substrate part 31CH₂ in the device region 31B ofthe substrate 31 obtained in FIG. 3B. In the substrate part 31CH₁, theleft and right side surfaces of the gate electrode 33G₁ carry therespective side wall insulating films 33SW₁ formed of a silicon nitridefilm via the side wall spacers 31GW₁ formed of a silicon nitride film.Likewise, in the substrate part 31CH₂, the left and right side surfacesof the gate electrode 33G₂ carry the respective side wall insulatingfilms 33SW₂ formed of a silicon nitride film via the side wall spacers31GW₂ formed of a silicon nitride film. Further, the gate electrode 33G₁carries a cap layer 33GN₁ formed of a silicon nitride film andsimilarly, the gate electrode 33G₂ carries a cap layer 33GN₂ formed of asilicon nitride film.

Note that in the fourth embodiment, the source extension region or thedrain extension region has been yet to be formed on the substrate part31CH₁ or 31CH₂ in the process of FIG. 7A.

Next, as illustrated in FIG. 7B, in the fourth embodiment, the siliconsubstrate 31 is dry etched to a depth range of 30 to 50 nm utilizingdevice isolation structures 31I₁ to 31I₃, the side wall insulating films33SW₁ and 33SW₂, the cap layers 33GN₁ and 33GN₂ as a mask. As a result,the trenches 31TA₁ and 31TA₂ are respectively formed on the left sideand right side of the substrate part 31CH₁, and the trenches 31TA₃ and31TA₄ are respectively formed on the left side and right side of thesubstrate part 31CH₂. Note that in the process of FIG. 7B, as a resultof dry etching, parts of the silicon substrate 31 may remain as aresidue 31 s in shadowed areas of the trapezoid device isolation regions31I₁ to 31I₃.

Next, as illustrated in FIG. 7C, the structure obtained in FIG. 7B issubject to thermal oxidation or plasma oxidation such that the bottomsurfaces and side surfaces of the trenches 31TA₁ to 31TA₄ are coveredwith silicon oxide films 41TOx₁ to 41TOx₄ each having a thickness rangeof, for example, 10 to 15 nm. Such silicon oxide films are also formedon the residues 31 s. Since the source extension region and the drainextension region are yet to be formed on the substrate parts 31CH₁ and31CH₂, the thermal oxidation process performed on the structure of FIG.7B will not deteriorate the properties of the semiconductor device.Further, the silicon oxide films 41TOx₁ to 41TOx₄ may be formed at 600°C. or lower by the plasma oxidation.

Next, as illustrated in FIG. 7D, the silicon oxide films 41TOx₁ to41TOx₄ covering the bottom surfaces of the trenches 31TA₁ to 31TA₄ areremoved by anisotropic etching that reacts approximately perpendicularto the main surface of the silicon substrate 31. Further, the siliconsubstrate 31 exposed from the bottom surfaces of the trenches 31TA₁ to31TA₄ is dry etched to a depth range of 30 to 50 nm as illustrated byarrows in FIG. 7D. As described earlier, the silicon oxide films 41TOx₁to 41TOx₄ are formed in a thickness range of 10 to 15 nm. Accordingly, asufficient thickness of the silicon oxide film may remain on the sidesurfaces of the trenches 31TA₁ to 31TA₄ even if the silicon oxide filmsare etched by anisotropic etching. The silicon substrate 31 is exposedfrom the bottom surfaces and the side surfaces of the etched parts inthe depth directions by dry etching (indicated by the arrows in FIG. 7D)of the trenches 31TA₁ to 31TA₄.

Further, as illustrated in FIG. 7E, the structure obtained in FIG. 7D issubject to isotropic wet etching utilizing tetramethyl ammoniumhydroxide (TMAH) as an etchant such that the silicon substrate 31exposed from the trenches 31TA₁ to 31TA₄ is further etched to the depthof approximately 10 nm.

As a result of such an isotropic wet etching, parts of the bottoms ofthe trenches 31TA₁ to 31TA₄, where an impurity element might have beenimplanted while dry etching, are removed. Accordingly, the siliconsurfaces of the initial high quality silicon substrate 31 are exposed.Thus, a subsequently performed epitaxial growth of the SiGe mixedcrystal layers may be promoted. In addition, in the process of FIG. 7D,due to the shadowed areas of the trapezoid device isolation regions 31I₁to 31I₃, silicon residues 31 t may remain at lower parts of the siliconoxide films 41TOx₁ to 41TOx₄ corresponding to the residues 31 s.However, such silicon residues 31 t may be completely removed a resultof such an isotropic wet etching. The technical significance of removingthe silicon residues 31 t will be described later in association withthe process of FIG. 7K.

Next, as illustrated in FIG. 7F, the SiGe mixed crystal layer isdeposited on the structure obtained in the process of FIG. 7E at atemperature range of 400 to 800° C. or preferably at a substratetemperature range of 500 to 600° C. by the CVD process utilizing a SiH₄gas and a GeH₄ gas as a source gas, a HCl gas as an etching gas and ahydrogen gas as a carrier gas. As a result, a SiGe mixed crystal layer31SG₁ epitaxially grows on the substrate 31 in the trench 31TA₁, a SiGemixed crystal layer 31SG₂ epitaxially grows on the substrate 31 in thetrench 31TA₂, a SiGe mixed crystal layer 31SG₃ epitaxially grows on thesubstrate 31 in the trench 31TA₃, and a SiGe mixed crystal layer 31SG₄epitaxially grows on the substrate 31 in the trench 31TA₄. The SiGemixed crystal layers 31SG₁ to 31SG₄ are selectively deposited with afilm thickness range of 20 to 80 nm corresponding to a desired thicknessof the oxide film pattern to be formed beneath the source region and thedrain region of the semiconductor device. For example, in the process ofFIG. 7F, the SiGe mixed crystal layers 31SG₁ to 31SG₄ may be depositedunder a pressure range of approximately 30 to 1500 Pa, with the hydrogengas being set in a partial pressure range of 30 to 1450 Pa, with theSiH₄ gas being set in a partial pressure range of 1 to 90 Pa, with theGeH₄ gas being set in a partial pressure range of 0.05 to 90 Pa and withthe HCl gas being set in a partial pressure range of 1 to 500 Pa.

Next, as illustrated in FIG. 7G, a silicon layer is deposited on thestructure obtained in FIG. 7F at a temperature range of 500 to 800° C.,or preferably a substrate temperature range of 500 to 600° C. by the CVDprocess utilizing a SiH₄ gas as a source gas, a HCl gas as an etchinggas and a hydrogen gas as a carrier gas. As a result, silicon epitaxiallayers 31ES are selectively deposited with a film thickness ofapproximately 7 nm on the SiGe mixed crystal layers 31SG₁ to 31SG₄. Forexample, in the process of FIG. 7G, the silicon epitaxial layers 31ESmay be deposited under a pressure range of approximately 30 to 1500 Pa,with the hydrogen gas being set in a partial pressure range of 30 to1450 Pa, with the SiH₄ gas being set in a partial pressure range of 1 to90 Pa and with the HCl gas being set in a partial pressure range of 1 to500 Pa.

Next, as illustrated in FIG. 7H, the silicon oxide films 41TOx₁ to41TOx₄ formed on the side surfaces of the trenches 31TA₁ to 31TA₄ areselectively removed by wet etching utilizing HF. In this case, thinsilicon epitaxial layers 31ES are initially formed on the SiGe mixedcrystal layers 31SG₁ to 31SG₄. In this manner, the exposed areas of theSiGe mixed crystal layers 31SG₁ to 31SG₄ may be limited and hence, thefabricating device may be prevented from being contaminated by Ge elutedby wet etching.

Next, as illustrated in FIG. 7I, the silicon epitaxial layers 31ES₁ to31ES₄ are deposited on the structure obtained in the process of FIG. 7Hat a temperature range of 500 to 800° C. or preferably at a substratetemperature range of 700 to 800° C. that is higher than the substratetemperature range for depositing the SiGe mixed crystal layers 31SG₁ to31SG₄ or the silicon epitaxial layers 31ES₁ to 31ES₄ by the CVD processutilizing a SiH₄ gas as a source gas, a HCl gas as an etching gas and ahydrogen gas as a carrier gas. As a result, a silicon epitaxial layer31ES₁ epitaxially grows on the SiGe mixed crystal layers 31SG₁ in thetrench 31TA₁, a silicon epitaxial layer 31ES₂ epitaxially grows on theSiGe mixed crystal layers 31SG₂ in the trench 31TA₂, a silicon epitaxiallayer 31ES₃ epitaxially grows on the SiGe mixed crystal layers 31SG₃ inthe trench 31TA₃, and a silicon epitaxial layer 31ES₄ epitaxially growson theSiGe mixed crystal layers 31SG₄ in the trench 31TA₄. Thus, thesilicon epitaxial layer 31ES₁ to 31ES₄ epitaxially grow on the siliconepitaxial layers 31ES beneath the silicon epitaxial layer 31ES₁ to 31ES₄so as to fill the trenches 31TA₁ to 31TA₄. Since the silicon epitaxiallayer 31ES₁ to 31ES₄ epitaxially grow on the previously siliconepitaxial layers 31ES that are located beneath the silicon epitaxiallayer 31ES₁ to 31ES₄, the silicon epitaxial layers 31ES are absorbed bythe respective silicon epitaxial layer 31ES₁ to 31ES₄ to become uniformsilicon epitaxial layer 31ES₁ to 31ES₄. Thus formed silicon epitaxiallayers 31ES₁ to 31ES₄ are epitaxially associated with the SiGe mixedcrystal layers 31SG₁ to 31SG₄ that are located beneath the siliconepitaxial layers 31ES₁ to 31ES₄. For example, in the process of FIG. 7I,the silicon epitaxial layers 31ES₁ to 31ES₄ may be deposited under apressure range of approximately 30 to 1500 Pa, with the hydrogen gasbeing set in a partial pressure range of 30 to 1450 Pa, with the SiH₄gas being set in a partial pressure range of 1 to 90 Pa and with the HClgas being set in a partial pressure range of 1 to 500 Pa.

In the fourth embodiment, the surfaces of the SiGe mixed crystal layers31SG₁ to 31SG₄ are covered with the thin silicon epitaxial layers 31ESin the process of FIG. 7G. Accordingly, even if the silicon epitaxiallayers 31ES₁ to 31ES₄ are thickly deposited at high temperatures in theprocess of FIG. 7I, the surfaces of the SiGe mixed crystal layers 31SG₁to 31SG₄ may be prevented from being damaged. As a result, thehigh-quality silicon epitaxial layers 31ES₁ to 31ES₄ may be obtained.

Note that in the process of FIG. 7I, the silicon epitaxial layers 31ES₁to 31ES₄ may grow beyond the interface between the silicon substrate 31and the gate insulating film 32 to thereby form a so-called “elevatedsource/drain structure”.

Next, as illustrated in FIG. 7J, device isolation films forming thedevice isolation structures 31I₁ to 31I₃ are depressed by wet etchingutilizing fluorinated acid or by dry etching of the silicon oxide filmin a similar manner as the process of FIG. 3K. As a result, the sidesurfaces of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄are exposed.

Note that in the process of FIG. 7J, the device isolation films formingthe device isolation structures 31I₁ to 31I₃ may be depressed inadvance, and then the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and31SG₄, and the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄may epitaxially grow thereafter.

Note that in the structure obtained in the process of FIG. 7J, the sidesurfaces of the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄,or the side surfaces of the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃and 31ES₄ may be formed of a single crystalline plane or pluralcrystalline planes.

Next, as illustrated in FIG. 7K, the SiGe mixed crystal layers 31SG₁,31SG₂, 31SG₃ and 31SG₄ are selectively etched from the silicon substrate31 and the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ by dryetching utilizing a mixed gas of chlorine (Cl₂) and hydrogen, orutilizing a hydrogen chloride gas, by wet etching utilizing a mixedsolution of fluorinated acid, nitric acid, acetic acid and the like, orby dry etching utilizing a tetrafluoromethane (CF₄) gas diluted by argon(Ar). Accordingly, voids 31V₁ to 31V₄ are formed in the regionscorresponding to the SiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and31SG₄ of the silicon substrate 31 in a similar manner as in the processof FIG. 3K.

Note that in the process of FIG. 7K, as described earlier, the siliconepitaxial layers 31ES₁ and 31ES₂ epitaxially lattice match the substratepart 31CH₁, and the silicon epitaxial layers 31ES₃ and 31ES₄ epitaxiallylattice match the substrate part 31CH₂. Accordingly, even if the SiGemixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄ are selectivelyremoved from the corresponding substrate parts 31CH₁ and 31CH₂, and thesilicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄, the siliconepitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄ will not fall off of thecorresponding substrate parts 31CH₁ or 31CH₂ of the silicon substrate31.

Further, if the etching process in FIG. 7K is performed by the dryetching, the device isolation structures 31I₁ to 31I₃ may be depressedby etching before the deposition of the SiGe mixed crystal layers 31SG₁,31SG₂, 31SG₃ and 31SG₄ and the silicon epitaxial layers 31ES₁, 31ES₂,31ES₃ and 31ES₄. In this manner, even if the device isolation structures31I₁ to 31I₃ are depressed by wet etching, the deposition process of theSiGe mixed crystal layers 31SG₁, 31SG₂, 31SG₃ and 31SG₄, the depositionprocess of the silicon epitaxial layers 31ES₁, 31ES₂, 31ES₃ and 31ES₄,and the selective etching process of FIG. 7K may be continuouslyperformed in the same process device without having to temporarilyremove the treating substrate from the process device in the middle ofthe above processes.

In the fourth embodiment, the SiGe mixed crystal layers 31SG₁ to 31SG₄may include the atomic fraction of Ge of approximately 20% similar tothe first embodiment. However, a large amount of Ge may be contained inthe SiGe mixed crystal layers 31SG₁ to 31SG₄ within a range of allowingthe SiGe mixed crystal layers 31SG₁ to 31SG₄ to epitaxially grow on thesurface of the silicon substrate 31, such as the SiGe mixed crystallayers 31SG₁ to 31SG₄ having the atomic fraction of Ge of approximately40%. Thus, the selectivity in the etching process of FIG. 7K may beimproved by utilizing SiGe mixed crystal a high concentration of Ge asthe SiGe mixed crystal layers 31SG₁ to 31SG₄. Further, SiGeC mixedcrystal may optionally be utilized as the SiGe mixed crystal layers31SG₁ to 31SG₄.

In the fourth embodiment, as described earlier, the silicon residues 31t (see FIG. 7D) formed of the side surfaces of the trenches 31TA₁ to31TA₄ in contact with the trapezoid device isolation regions 31I₁ to31I₃ are selectively removed by wet etching in the process of FIG. 7E.As a result of having removed the silicon residues 31 t in this manner,openings (i.e., voids) 31 v ₁ to 31 v ₄ of the voids 31V₁ to 31V₄ willnot be blocked by the silicon residues 31 t when the SiGe mixed crystallayer 31SG₁ to 31SG₄ are removed in the process of FIG. 7K. Accordingly,the SiGe mixed crystal layer 31SG₁ to 31SG₄ may be efficiently etched.

Next, as illustrated in FIG. 7L, an embedded insulating film 41I_(E)formed of a silicon oxide film or a silicon nitride film as a majorcomponent is deposited on the structure obtained in the process of FIG.7K by a deposition process exhibiting excellent step coverage, such asthe ALD process, the CVD process, or the SOG process. Accordingly, thevoids 31V₁ to 31V₄ are filled with embedded insulating film 41I_(E). Inthe example of FIG. 7L, the embedded insulating film 41I_(E) isdeposited by a high density plasma-CVD (HDP-CVD) process. Note that inthe fourth embodiment, the voids 31V₁ to 31V₄ may not have to becompletely filled with the embedded insulating film 41I_(E), and thevoids 31V₁ to 31V₄ filled with the embedded insulating film 41I_(F) maypartially have unfilled parts (i.e., spaces).

Next, as illustrated in FIG. 7M, the embedded insulating film 41I_(F) isplanarized by a chemical mechanical polishing (CMP) or an etch backprocess. Further, as illustrated in FIG. 7N, the embedded insulatingfilm 41I_(E) is etched by HF such that the side wall insulating films33SW₁ and 33SW₂ are exposed while the surfaces of the silicon epitaxiallayers 31ES₁ to 31ES₄ being covered with the embedded insulating film41I_(F).

Further, as illustrated in FIG. 7O, the side wall insulating films 33SW₁and 33SW₂ formed of the silicon nitride films are etched by wet etchingutilizing phosphoric acid (H₃PO₄) as an etchant, and subsequently, theobtained structure is processed by HF again to expose the siliconepitaxial layers 31ES₁ to 31ES₄ in the process of FIG. 7P.Simultaneously, in this process, the side wall spacers 33GW₁ and 33GW₂of the gate electrodes 31G₁ and 32G₂ are removed.

After having performed the process of FIG. 7P, the fabrication processesof the ordinary MOS transistor are conducted. Specifically, boron (B) isimplanted in the silicon epitaxial layers 31ES₁ and 31ES₂ utilizing thegate electrode 33G₁ as a mask while the device region 31B is coveredwith the resist mask (not illustrated). As a result, a p-type sourceextension region 31 a and a p-type drain extension region 31 b areformed. Similarly, arsenic (As) or phosphorus (P) is implanted in thesilicon epitaxial layers 31ES₃ and 31ES₄ utilizing the gate electrode33G₂ as a mask while the device region 31A is covered with the resistmask (not illustrated). As a result, an n-type source extension region31 c and an n-type drain extension region 31 d are formed.

Further, as illustrated in FIG. 7Q, the side wall insulating films 43SW₁and 43SW₂ formed of a silicon oxide film or a silicon nitride film areformed on the gate electrode 31G₁ and 31G₂. Subsequently, as illustratedin FIG. 7R, boron (B) is implanted in the silicon epitaxial layers 31ES₁and 31ES₂ utilizing the gate electrode 33G₁ and the side wall insulatingfilms 43SW₁ as a mask while the device region 31B is covered with theresist mask (not illustrated). As a result, a p-type source region 31 eand a p-type drain region 31 f are formed. Similarly, arsenic (As) orphosphorus (P) is implanted in the silicon epitaxial layers 31ES₃ and31ES₄ utilizing the gate electrode 33G₂ and the side wall insulatingfilms 43SW₂ as a mask while the device region 31A is covered with theresist mask (not illustrated). As a result, an n-type source region 31 cand an n-type drain region 31 d are formed.

Note that in the fourth embodiment, an additional process, in whichisotropic etching is performed on the structure obtained in FIG. 7B byutilzinig TMAH to extend (widen) the trenches 31TA₁ to 31TA₄ asindicated by arrows in FIG. 8A, may be carried out between the processof FIG. 7B and the process of FIG. 7C. In the process of FIG. 8A, theside surfaces of the trenches 31TA₁ to 31TA₄ that form the substratepart 31CH₁ may be depressed and at the same time, the silicon residues21 s may be removed.

In such a modification, if the silicon oxide films 41TOx₁ to 41TOx₄ areformed by performing the oxidation process of FIG. 8B corresponding tothe process of FIG. 7C, the silicon oxide films formed on the depressedside surfaces of the trenches 31TA₁ to 31TA₄ are protected by the sidewall insulating film 33SW₁ or 33SW₂ of the gate electrode 33GN₁ or33GN₂. Accordingly, even if the subsequently performed dry etching ofFIG. 7D includes obliquely incident radicals, the silicon oxide films41TOx₁ to 41TOx₄ will not be removed. Thus, the growth of the SiGe mixedcrystal layers on the side surfaces of the trenches 31TA₁ to 31TA₄ maybe reliably prevented.

According to the embodiments, even if the first and the secondsemiconductor layers formed beneath the third and the fourthsemiconductor layers are selectively removed to form the voids, thethird and the fourth semiconductor layers may still be supported and maynot collapse due to the third and the fourth semiconductor layersrespectively forming the source region and the drain region being bondedwith the side surfaces of the first and the second trenches that formthe semiconductor substrate. Accordingly, the voids may be filled withthe embedded insulating film to form a semiconductor device locallyhaving the SOI structure in the source region and the drain region.

Note that the modification of the fourth embodiment illustrated in FIGS.8A and 8B may also be applicable to the first to the third embodiments.

The embodiments described so far are not limited thereto. Variousmodifications or alterations may be made within the scope of theinventions described in the claims.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority orinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatvarious changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. A semiconductor device comprising: a semiconductor substrateincluding a well having a first conductivity type, the well beingdefined by a device isolation region; a gate insulating film formed onthe semiconductor substrate; a gate electrode formed on the gateinsulating film, the gate electrode including a first side surface and asecond side surface facing the first side surface; and a first side wallinsulating film formed on the first side surface and a second side wallinsulating film formed on the second side surface, wherein thesemiconductor substrate includes a mesa structure located below thefirst side wall insulating film, the gate electrode and the second sidewall insulating film, the mesa structure includes a first side surfaceand a second side surface, a first semiconductor layer having the secondconductivity type that form a source region is formed outside of thefirst side surface of the mesa structure, with the first semiconductorlayer being connected to the semiconductor substrate on the first sidesurface, a second semiconductor layer having the second conductivitytype that form a drain region is formed outside of the second sidesurface of the mesa structure, with the second semiconductor layer beingconnected to the semiconductor substrate on the second side surface, afirst embedded insulating region formed of a first insulating film isformed beneath the first semiconductor layer and a second embeddedinsulating region formed of the first insulating film is formed beneaththe second semiconductor layer, and a second insulating film is formedbetween the first embedded insulating region and the first side surfaceof the mesa structure, and a third insulating film is formed between thesecond embedded insulating region and the second side surface of themesa structure.
 2. The semiconductor device as claimed in claim 1,wherein the second insulating film and the third insulating film have athickness equal to or greater than 2 nm and equal to or smaller than 10nm.
 3. The semiconductor device as claimed in claim 1, wherein an uppersurface of the second insulating film is lower than an upper surface ofthe first embedded insulating region, and an upper surface of the thirdinsulating film is located lower than an upper surface of the secondembedded insulating region.
 4. The semiconductor device as claimed inclaim 1, wherein the first insulating film includes a compositiondiffering from a composition of the second and the third insulatingfilms.
 5. The semiconductor device as claimed in claim 1, wherein thefirst insulating film is a silicon oxide film, and the second and thethird insulating films are formed of one of a silicon oxide film, asilicon nitride film and a silicon oxynitride film.
 6. The semiconductordevice as claimed in claim 1, wherein the first insulating film is asilicon oxide film formed by a chemical vapor deposition process, andthe second and the third insulating films are a silicon oxide filmformed by one of a thermal oxidation process, a plasma oxidation processand a chemical vapor deposition process.
 7. A method for fabricating asemiconductor device, the method comprising: forming a gate electrode ona first region of a semiconductor substrate formed of a firstsemiconductor, forming a first side wall insulating film on a first sidesurface of the gate electrode and forming a second side wall insulatingfilm on a second side surface of the gate electrode; forming a firstopening part and a second opening part with the first region interposedtherebetween; forming a first insulating film on side surfaces and abottom surface of the first opening part and also on side surfaces and abottom surface of the second opening part; removing the first insulatingfilm while allowing at least parts of the first insulating film toremain on the side surfaces of the first and the second opening parts;forming a first semiconductor layer and a second semiconductor layer inthe first opening part and the second opening part, respectively, thefirst and the second semiconductor layers being formed of a secondsemiconductor having etching selectivity to the first semiconductor;removing the first insulating film from the side surface of the firstopening part and also from the side surface of the second opening part;forming a third semiconductor layer and a fourth semiconductor layer onthe first semiconductor layer and the second semiconductor layer,respectively, after having removed the first insulating film from theside surface of the first opening part and also from the side surface ofthe second opening part, the third and the fourth semiconductor layersbeing formed of the first semiconductor; exposing respective parts ofthe first semiconductor layer and the second semiconductor layer afterhaving formed the third semiconductor layer and the fourth semiconductorlayer on the first semiconductor layer and the second semiconductorlayer, respectively; removing the first and second semiconductor layersto form a third opening part and a fourth opening part after havingexposed the respective parts of the first semiconductor layer and thesecond semiconductor layer; forming a second insulating film in thethird opening part and the fourth opening part; and implanting animpurity element in the third semiconductor layer and the fourthsemiconductor layer to form a first diffusion region and a seconddiffusion region, respectively.
 8. The method as claimed in claim 7,further comprising: performing isotropic etching on the first openingpart and the second opening part to depress the side surfaces of thefirst and the second opening parts, the isotropic etching beingperformed after having formed the first and the second opening parts andbefore forming the first insulating film.
 9. The method as claimed inclaim 7, wherein forming the first and the second opening partsincludes: forming a first device isolation trench and a second deviceisolation trench in the semiconductor substrate; forming a thirdinsulating film in each of the first device isolation trench and thesecond device isolation trench to form a first device isolation regionand a second isolation region, respectively; and forming the firstopening part and the second opening part to contact with the firstdevice isolation region and the second isolation region, respectively,wherein exposing the first and the second semiconductor layers includes:removing the third insulating film from the first device isolationregion and the second isolation region to form respective openings inthe first device isolation trench and the second device isolation trenchsuch that the first and the second semiconductor layers are exposed, andwherein forming the second insulating film in the third opening part andthe fourth opening part includes: forming, after having removed thethird insulating film from the first device isolation trench and thesecond device isolation trench to form openings of the first deviceisolation trench and the second device isolation trench, the secondinsulating film in the openings of the first device isolation trench andthe second device isolation trench.
 10. The method as claimed in claim7, wherein exposing the respective parts of the first semiconductorlayer and the second semiconductor layer includes: covering the thirdsemiconductor layer and the fourth semiconductor layer with a maskpattern; and etching the third semiconductor layer and the fourthsemiconductor layer to form the first device isolation trench and thesecond device isolation trench, respectively, such that the first andthe second semiconductor layers are exposed, and wherein forming thesecond insulating film in the third opening part and the fourth openingpart includes: forming the second insulating film in the first deviceisolation trench and the second device isolation trench.
 11. The methodas claimed in claim 7, wherein the first insulating film is a siliconoxide film formed by one of a thermal oxidation process, a plasmaoxidation process and a chemical vapor deposition process.
 12. Themethod as claimed in claim 7, further comprising: forming a fifthsemiconductor layer and a sixth semiconductor layer on the firstsemiconductor layer and the second semiconductor layer, respectively,before removing the first insulating film from the side surface of thefirst opening part and also from the side surface of the second openingpart, the first insulating film being removed from the side surface ofthe first opening part and the side surface of the second opening partafter having formed the first semiconductor layer and the secondsemiconductor layer.
 13. The method as claimed in claim 7, furthercomprising: etching the bottom surfaces of the first opening part andthe second opening part before forming the first semiconductor layer andthe second semiconductor layer, the first semiconductor layer and thesecond semiconductor layer being formed after having removed the firstinsulating layer from the bottom surfaces of the first opening part andthe second opening part.
 14. The method as claimed in claim 13, whereinetching the bottom surfaces of the first opening part and the secondopening part includes: anisotropically etching the bottom surfaces ofthe first opening part and the second opening part; and isotropicallyetching the bottom surfaces of the first opening part and the secondopening part after having anisotropically etched the bottom surfaces ofthe first opening part and the second opening part.
 15. The method asclaimed in claim 7, wherein removing the first insulating film from theside surface of the first opening part and from the side surface of thesecond opening part includes: removing the first insulating film fromthe side surface of the first opening part and from the side surface ofthe second opening part, excluding at least a part between the firstsemiconductor layer and the side surface of the first opening part andat least apart between the second semiconductor layer and the sidesurface of the second opening part.
 16. The method as claimed in claim7, wherein forming the first and the second opening parts includes:etching the semiconductor substrate utilizing the first side wallinsulating film and the second side wall insulating film as a mask. 17.The method as claimed in claim 7, further comprising: forming a gateelectrode in the first region after having formed the second insulatingfilm in the third opening part and the fourth opening part; and formingthe first side wall insulating film on the first side surface of thegate electrode and the second side wall insulating film on the secondside surface of the gate electrode.